參數(shù)資料
型號(hào)： AD7706BRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
中文描述： 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： MO-153AB, TSSOP-16
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 264K
代理商： AD7706BRU
AD7705/AD7706
–15–
REV. A
CIRCUIT DESCRIPTION
The AD7705/AD7706 is a sigma-delta A/D converter with on-
chip digital filtering, intended for the measurement of wide
dynamic range, low frequency signals such as those in industrial
control or process control applications. It contains a sigma-delta
(or charge-balancing) ADC, a calibration microcontroller with
on-chip static RAM, a clock oscillator, a digital filter and a bi-
directional serial communications port. The part consumes only
320
μ
A of power supply current, making it ideal for battery-
powered or loop-powered instruments. These parts operate with
a supply voltage of 2.7 V to 3.3 V or 4.75 V to 5.25 V.
The AD7705 contains two programmable-gain fully differential
analog input channels, while the AD7706 contains three pseudo
differential analog input channels. The selectable gains on these
inputs are 1, 2, 4, 8, 16, 32, 64 and 128 allowing the part to
accept unipolar signals of between 0 mV to +20mV and 0 V to
+2.5V, or bipolar signals in the range from
±
20mV to
±
2.5V
when the reference input voltage equals +2.5V. With a refer-
ence voltage of +1.225V, the input ranges are from 0 mV to
+10mV to 0 V to +1.225V in unipolar mode, and from
±
10mV
to
±
1.225 V in bipolar mode. Note that the bipolar ranges are
with respect to AIN(–) on the AD7705, and with respect to
COMMON on the AD7706, and not with respect to GND.
The input signal to the analog input is continuously sampled
at a rate determined by the frequency of the master clock,
MCLKIN, and the selected gain. A charge-balancing A/D
converter (Sigma-Delta Modulator) converts the sampled signal
into a digital pulse train whose duty cycle contains the digital
information. The programmable gain function on the analog
input is also incorporated in this sigma-delta modulator with the
input sampling frequency being modified to give the higher
gains. A sinc
3
digital low-pass filter processes the output of the
sigma-delta modulator and updates the output register at a rate
determined by the first notch frequency of this filter. The out-
put data can be read from the serial port randomly or periodi-
cally at any rate up to the output register update rate. The first
notch of this digital filter (and hence its –3dB frequency) can
be programmed via the Setup Register bits FS0 and FS1. With
a master clock frequency of 2.4576MHz, the programmable
range for this first notch frequency is from 50Hz to 500Hz,
giving a programmable range for the –3dB frequency of
13.1Hz to 131Hz. With a master clock frequency of 1MHz,
the programmable range for this first notch frequency is from
20Hz to 200Hz, giving a programmable range for the –3dB
frequency of 5.24Hz to 52.4Hz.
The basic connection diagram for the AD7705 is shown in
Figure 10. This shows the AD7705 being driven from the ana-
log +5V supply. An AD780, precision +2.5 V reference, pro-
vides the reference source for the part. On the digital side, the
part is configured for three-wire operation with
CS
tied to
GND. A quartz crystal or ceramic resonator provide the master
clock source for the part. In most cases, it will be necessary to
connect capacitors on the crystal or resonator to ensure that it
does not oscillate at overtones of its fundamental operating fre-
quency. The values of capacitors will vary, depending on the
manufacturer’s specifications. The same setup applies to the
AD7706.
V
DD
ANALOG
+5V SUPPLY
10
m
F
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
DIFFERENTIAL
ANALOG
INPUT
DIFFERENTIAL
ANALOG
INPUT
GND
REF IN(+)
REF IN(–)
10
m
F
V
IN
ANALOG +5V
SUPPLY
AD780/
REF192
V
OUT
GND
AD7705
DRDY
DATA READY
DOUT
RECEIVE (READ)
DIN
SERIAL DATA
SCLK
SERIAL CLOCK
RESET
+5V
CS
MCLK IN
MCLK OUT
CRYSTAL OR
CERAMIC
RESONATOR
0.1
m
F
0.1
m
F
Figure 10. AD7705 Basic Connection Diagram
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