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參數(shù)資料
| 型號： | AD7699BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8CH 16BIT 500KSPS 20LFCSP |
| 標準包裝： | 1,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極；4 個差分，雙極；4 個偽差分，雙極 |
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AD7699
Data Sheet
Rev.
| Page 16 of 28
Unipolar or Bipolar
Figure 27 shows an example of the recommended connection
diagram for the AD7699 when multiple supplies are available.
Bipolar Single Supply
Figure 28 shows an example of a system with a bipolar input
using single supplies with the internal reference (optional
different VIO supply). This circuit is also useful when the
amplifier/signal conditioning circuit is remotely located with
some common mode present. Note that for any input config-
uration, the inputs, INx, are unipolar and always referenced to
GND (no negative voltages even in bipolar range).
For this circuit, a rail-to-rail input/output amplifier can be used;
however, the offset voltage vs. input common-mode range should
be noted and taken into consideration (1 LSB = 62.5 μV with
VREF = 4.096 V). Note that the conversion results are in twos
complement format when using the bipolar input configuration.
Refer to the AN-581 Application Note, Biasing and Decoupling
Op Amps in Single Supply Applications, at www.analog.com for
additional details about using single-supply amplifiers.
ANALOG INPUTS
Input Structure
Figure 29 shows an equivalent circuit of the input structure of
the AD7699. The two diodes, D1 and D2, provide ESD
protection for the analog inputs, IN[7:0] and COM. Care must
be taken to ensure that the analog input signal does not exceed
the supply rails by more than 0.3 V because this causes the
diodes to become forward-biased and to start conducting
current.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions may eventually occur
when the input buffer supplies are different from VDD. In such
a case, for example, an input buffer with a short circuit, the
current limitation can be used to protect the part.
CIN
RIN
D1
D2
CPIN
INx+
OR INx–
OR COM
GND
VDD
07
35
4-
0
27
Figure 29. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true
differential signal between INx+ and COM or INx+ and INx.
(COM or INx = GND ± 0.1 V or VREF ± 0.1 V). By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 30.
70
65
60
55
50
45
40
35
30
1
10k
10
CM
RR
(
d
B)
100
1k
FREQUENCY (kHz)
07
35
4-
02
8
Figure 30. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog inputs
can be modeled as a parallel combination of the capacitor, CPIN,
and the network formed by the series connection of RIN and CIN.
CPIN is primarily the pin capacitance. RIN is typically 400 Ω (8.8 kΩ
when the one-pole filter is active) and is a lumped component
made up of serial resistors and the on resistance of the switches.
CIN is typically 27 pF and is mainly the ADC sampling capacitor.
Selectable Low-Pass Filter
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. While the AD7699 is
acquiring, RIN and CIN make a one-pole, low-pass filter that
reduces undesirable aliasing effects and limits the noise from
the driving circuitry. The low-pass filter can be programmed
for the full bandwidth or of the bandwidth with CFG[6], as
shown in Table 8. Note that the converter throughput must also be
reduced by when using the filter. If the maximum throughput
is used with the BW set to , the acquisition time of the
converter, tACQ, is violated, resulting in poor THD.
Input Configurations
Figure 31 shows the different methods for configuring the analog
inputs with the configuration register (CFG[12:10]). Refer to
the Configuration Register, CFG section for more details.
B
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