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參數(shù)資料
| 型號(hào)： | AD7691 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN |
| 中文描述： | 18位，1.5 LSB INL和250 kSPS的PulSAR系列差分ADC，采用MSOP / QFN封裝 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 682K |
| 代理商： | AD7691 |
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AD7691
The AD7691 powers down automatically at the end of each
conversion phase, and therefore the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (as low as a few hertz) and low battery-powered applications.
Rev. 0 | Page 17 of 28
1000
10
0.1
0.001
10
1M
SAMPLING RATE (SPS)
O
100
1k
100k
10k
VDD = 5V
VIO
0
Figure 32. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7691, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 33.
AD8031
AD7691
VIO
REF
VDD
10μF
1μF
10
10k
5V
5V
5V
1μF
1
1
OPTIONAL REFERENCE BUFFER AND FILTER.
0
Figure 33. Example of an Application Circuit
DIGITAL INTERFACE
Though the AD7691 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7691 is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Black
fin
ADSP-BF53x or
ADSP-219x. In this mode, the AD7691 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
When in chain mode, the AD7691 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
In either mode, the AD7691 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
The busy indicator feature is enabled
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 37 and Figure 41).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 45).
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