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參數(shù)資料
| 型號： | AD768ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 30MSPS 28-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設置時間： | 25ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 600mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 40M |
REV. B
–10–
AD768
APPLYING THE AD768
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configura-
tions for the AD768. While most figures take the output at
IOUTA, IOUTB can be interchanged in all cases. Unless other-
wise noted, it is assumed that IREFIN and full-scale currents are
set to nominal values.
For application that require the specified dc accuracies, proper
resistor selection is required. In addition to absolute resistor tol-
erances, resistor self-heating can result in unexpected errors. For
optimal INL, the buffered voltage output is recommended as
shown in Figure 23. In this configuration, self-heating of RFB
may cause a change in gain, producing a bow in the INL curve.
This effect can be minimized by selection of a low temperature
coefficient resistor.
UNBUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Figure 21 shows the AD768 configured to provide a unipolar
output range of approximately 0 V to –1 V. The nominal full-
scale current of 20 mA flows through the parallel combination
of the 50
R
L resistor and the 1 k DAC output resistance
(from the R-2R ladder), for a combined 47.6
. This produces
an ideal full-scale voltage of –0.952 V with respect to LADCOM.
In addition, the 1 k
DAC output resistance has a tolerance of
±20% which may vary the full-scale gain by ±1%. This linear
variation results in a gain error which can be easily compensated
for by adjusting IREFIN.
1
27
28
VA
VB
AD768
RL
49.9
RL
49.9
IOUTA
LADCOM
IOUTB
Figure 21. 0 V to –1 V Unbuffered Voltage Output
In this configuration, it is important to note the restrictions from
the output compliance limits. The maximum negative voltage
compliance is –1.2 V, prohibiting use of a 100
load to produce
a 0 V to –2 V output swing. One additional consideration for
operation in this mode is integral nonlinearity. As the voltage at
the output node changes, the finite output impedance of the
DAC current steering switches gives rise to small changes in the
output current that vary with output voltage, producing a bow
(up to 8 LSBs) in the INL. For optimal INL performance, the
buffered voltage output mode is recommended.
The INL is also slightly dependent on the termination of the
unused output (IOUTB) as described in the ANALOG OUT-
PUT section. To eliminate this effect, IOUTB should be termi-
nated with the same impedance as IOUTA, so both outputs see
the same resistive divider to ground. This will keep the current
in LADCOM constant, minimizing any code-dependent IR
drops within the DAC ladder that may give rise to additional
nonlinearities.
AC-Coupled Output
Configuring the output as shown in Figure 22 provides a bipolar
output signal from the AD768 without requiring the use of a
summing amplifier. The ac load impedance presented to the
DAC output is the parallel combination of the AD768’s output
impedance, RL, and bias resistor RB. The nominal output swing
with the values given in Figure 22 is
±0.5 V assuming R
B >> RL.
The gain of the circuit will be a function of the tolerances of the
impedances RLAD, RB, and RL.
Choosing the value of RB and C will depend primarily on the
desired –3 dB high pass cutoff frequency and the bias current,
IB, of the subsequent stage connected to RB. The –3 dB fre-
quency can be approximated by the equation,
f–3 dB = 1/[2
× π × (R
B + RL RLAD)
× C].
The dc offset of the output is a function of the bias current of
the subsequent stage and the value of RB. For example, if
C = 390 pF, RB = 20 k, and IB = 1.0 A, the –3 dB frequency
is approximately 20.4 kHz and the dc offset would be 20 mV.
1
27
28
RB
AD768
RL
49.9
IOUTA
LADCOM
IOUTB
RL
49.9
IB
C
Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output
BUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Unipolar Configuration
For positive output voltages, or voltage ranges greater than
allowed by output compliance limits, some type of external
buffer is needed. A wide variety of amplifiers may be selected
based on considerations such as speed, accuracy and cost. The
AD9631 is an excellent choice when dynamic performance is
important, offering low distortion up to 10 MHz. Figure 23
shows the implementation of 0 V to +2 V full-scale unipolar
buffered voltage output. The amplifier establishes a summing
node at ground for the DAC output. The buffered output volt-
age results from the DAC output current flowing through the
amplifier’s feedback resistor, RFB. In this case, the 20 mA full-
scale current across RFB (100
) produces an output voltage
range of 0 V through +2 V. The same configuration using a pre-
cision amplifier such as the AD845 is recommended for optimal
dc linearity.
1
27
28
AD768
RFB
100
IOUTA
LADCOM
IOUTB
A1
Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output
Buffered Output Using a Current Divider
The configuration shown in Figure 23 may not be possible in
cases where the amplifier cannot supply the requisite 20 mA
feedback current. As an alternative, Figure 24 shows amplifier
A1 in conjunction with a resistive current divider. The values of
RFF and RL are chosen to limit the current, I3, which must be
supplied by A1. Current, I2, is shunted to ground through resis-
tor, RL. The parallel combination of RFF and RL should not ex-
ceed 60
to avoid exceeding the specified compliance voltage.
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