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參數資料
| 型號： | AD768AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Bit, 30 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.025 us SETTLING TIME, 16-BIT DAC, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數： | 8/20頁 |
| 文件大?。?/td> | 334K |
| 代理商： | AD768AR |
REV. B
–8–
AD768
DIGITAL INPUT CODE – k
8
–80
65
10
20
30
40
4
–2
–4
–6
6
0
2
D
50
60
5
15
25
35
45
55
Figure 9. Typical DNL Performance
T he outputs have a compliance range of –1.2 V to +5.0 V with
respect to LADCOM. T he current steering output stages will
remain functional over this range. Operation beyond the maxi-
mum compliance limits may cause either output stage saturation
or breakdown, resulting in nonlinear performance. T he rated dc
and ac performance specifications are for an output voltage of
0 V to –1 V.
T he current in LADCOM is proportional to I
REFIN
and has been
carefully configured to be independent of digital code when the
output is connected to a virtual ground. T his minimizes any det-
rimental effects of ladder ground resistance on linearity. For
optimal dc linearity, IOUT A should be connected directly to a
virtual ground, and IOUT B should be grounded. An example of
this configuration is provided in the section “Buffered Voltage
Output.” If IOUT A is driving a resistive load directly, then
IOUT B should be terminated with an equal impedance. T his
will ensure the current in LADCOM remains constant with digi-
tal code, and is recommended for improved dc linearity in the
unbuffered voltage output configuration.
As shown in Figure 10, there is an equivalent output impedance
of 1 k
in parallel with 3 pF at each output terminal. If the out-
put voltage deviates from the ladder common voltage, an error
current flows through this 1 k
impedance. T his is a linear effect
which does not change with input code, so it appears as a gain
error. With 50
output termination, the resulting gain error is
approximately –5%. An example of this configuration is pro-
vided in the section Unbuffered Voltage Output.
1
26
27
28
1k
1k
3pF
3pF
I
OUT
I
OUT
IREFIN
x2.75
V
EE
LADCOM
IOUTB
IOUTA
Figure 10. Equivalent Analog Output Circuit
DIGIT AL INPUT S
T he AD768 digital inputs consist of 16 data input pins and a
clock pin. T he 16-bit parallel data inputs follow standard posi-
tive binary coding, where DB15 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUT A pro-
duces full-scale output current when all data bits are at logic 1.
IOUT B is the complementary output, with full-scale when all
data bits are at logic 0. T he full-scale current is split between
the two outputs as a function of the input code.
T he digital interface is implemented using an edge-triggered
master slave latch. T he DAC output is updated following the
rising edge of the clock, and is designed to support a clock rate
as high as 40 MSPS. T he clock can be operated at any duty
cycle that meets the specified minimum latch pulse width. T he
setup and hold times can also be varied within the clock cycle as
long as the specified minimums are met, although the location
of these transition edges may affect digital feedthrough. T he
digital inputs are CMOS compatible with logic thresholds set to
approximately half the positive supply voltage. T he small input
current requirements allow for easy interfacing to unbuffered
CMOS logic. Figure 11 shows the equivalent digital input
circuit.
V
CC
V
EE
DIGITAL
INPUT
V
CC
DCOM
Figure 11. Equivalent Digital Input Circuit
Digital input signals to the DAC should be isolated from the
analog output as much as possible. Interconnect distances to the
DAC inputs should be kept as short as possible. T ermination
resistors may improve performance if the digital lines become
too long. T o minimize digital feedthrough, the inputs should be
free from glitches and ringing, and may be further improved
with a reduction of edge speed.
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