參數(shù)資料
型號(hào)： AD7685ARMZRL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT PSEUDO-DIFF 10MSOP
產(chǎn)品培訓(xùn)模塊： Power Line Monitoring
Motor Control
設(shè)計(jì)資源： Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
標(biāo)準(zhǔn)包裝： 1,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 15mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)偽差分，單極
配用： EVAL-AD7685CBZ-ND - BOARD EVAL FOR AD7685
AD7685
Rev. C | Page 23 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy chain multiple AD7685s on
a 3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7685s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
Figure 44) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7685 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N + 1
clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host also
using the SCK falling edge allows a faster reading rate and,
consequently, more AD7685s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 5 ns
digital host setup time and 3 V interface, up to eight AD7685s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
02
96
8-
04
2
CNV
SCK
SDO
SDI
AD7685
C
CNV
SCK
SDO
SDI
AD7685
A
CNV
SCK
SDO
SDI
AD7685
B
Figure 44. Chain Mode with BUSY Indicator Connection Diagram
SDOA = SDIB
DA15 DA14 DA13
SCK
12
3
35
47
48
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
415
tSCK
tSCKH
tSCKL
DA0
17
34
16
SDOB = SDIC
DB15 DB14 DB13
DA1
DB1DB0DA15 DA14
49
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC15 DC14 DC13
DA1DA0
DC1DC0DA14
19
31
32
18
33
DB1DB0DA15
DB15 DB14
tDSDOSDI
tSSCKCNV
tHSCKCNV
0
29
68
-04
3
DA0
tDSDOSDI
Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing
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