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參數(shù)資料
| 型號(hào)： | AD7684BRMRL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS PulSAR Differential ADC in MSOP |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 452K |
| 代理商： | AD7684BRMRL7 |
AD7684
Table 9. Recommended Driver Amplifiers
Amplifier
Typical Application
AD8021
Very low noise and high frequency
AD8022
Low noise and high frequency
OP184
Low power, low noise, and low frequency
AD8605
,
AD8615
5 V single-supply, low power
AD8519
Small, low power, and low frequency
AD8031
High frequency and low power
Rev. 0 | Page 14 of 16
VOLTAGE REFERENCE INPUT
The AD7684 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
When REF is driven by a very low impedance source (e.g., an unbuffered reference voltage like the low temperature drift
ADR43x
reference or a reference buffer using the
AD8031
or
the
AD8605
), a 10 μF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7684 powers down automatically at the end of each
conversion phase and therefore the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
0.01
0.1
1
10
100
1000
100
10
1k
10k
100k
SAMPLING RATE (SPS)
O
μ
A
0
VDD = 5V
VDD = 2.7V
Figure 24. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7684 is compatible with SPI, QSPI, digital hosts, and
DSPs (e.g., Blackfin ADSP-BF53x or ADSP-219x). The con-
nection diagram is shown in Figure 25 and the corresponding
timing is given in Figure 2.
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
OUT
is enabled and
forced low. The data bits are then clocked MSB first by subse-
quent DCLOCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time.
0
CS
DCLOCK
D
OUT
DATA IN
CLK
CONVERT
DIGITAL HOST
AD7684
Figure 25. Connection Diagram
LAYOUT
The printed circuit board housing the AD7684 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7684 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7684 is used as a shield. Fast switching signals, such as CS or
clocks, should never run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7684.
The AD7684 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7684 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7684. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
EVALUATING THE AD7684’S PERFORMANCE
Other recommended layouts for the AD7684 are outlined in the
evaluation board for the AD7684 (
EVAL-AD7684
). The evalua-
tion board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
EVAL-CONTROL BRD2
.
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| AD7684BRMZ | 功能描述:IC ADC 16BIT 100KSPS DIFF 8MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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