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參數(shù)資料
| 型號(hào)： | AD768-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 30 MSPS D/A Converter |
| 中文描述： | 16位，30 MSPS的D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大小： | 334K |
| 代理商： | AD768-EB |
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REV. B
–16–
AD768
T able III. Summary of Jumper Functionality
Installed
Jumper Function
Jumper
JP1
JP2
JP3 (ST BY)
JP4
JP5
Buffered Output A
50
T ransformer Output
Unbuffered Output A
Unbuffered Output B
Buffered Output B
T able IV. AD768-E B Parts List
Reference
Value / Part T ype Package
Qty/Bd
U1
AD768
28-Pin SOIC
1
U2
AD811
8-Pin DIP
1
T 1
Mini-Circuits
T 4–6T
Not Installed
1
A, B, CLOCK
BNC JACK s,
Small
Small, Vertical
3
JP1–5
Header
2-Pin
5
SW1, 2
SPDT , Secme
0.1"
×
0.3"
2
J1
40-Pin IDC
Connector
R.A., Male,
w/ Latches
1
R1
500
1/4 W, 0.01%,
Vishay
1
R2
25
1/4 W, 0.01%,
Vishay
1
R3, R13–21, &
R23–29
Wire Jumpers
17
R5
500
1/4 W, 0.01%,
Vishay
1
R7
100
1/4 W, 0.01%,
Vishay
1
R11
51
1/8 W, 5%, Carbon
1
R12
10 k
Pot.
3266 W
1
C1–4
1
μ
F Ceram. Cap.
Leaded
4
C5–8, C10, 12,
14, & C16–19
0.1
μ
F Chip Cap,
1206
11
C9, 11, 13, 15
22
μ
F T ant. Cap.,
25 V
T eardrop,
0.1" Spacing
4
Clock Input
An external sample clock must be provided to either the BNC
connector labeled “CLOCK ” or on Pin 33 of the IDC connec-
tor. T his clock must comply with the logic levels outlined in the
AD768 data sheet. T he “CLOCK ” input is terminated with a
removable 51
resistor. T he IDC connector clock connection
is unterminated.
SW1.
Clock source select switch. When SW1 is in position 1, Pin
33 of the IDC connected is applied to the CLOCK input of the
AD768. When SW2 is in position 2, the “CLOCK ” BNC connec-
tor is applied to the CLOCK input of the AD768.
Digital Inputs
T he digital inputs of the AD768, DB0–DB15, are available via
J1, a 40-pin IDC connector. T hese inputs should comply with
the specifications given in the AD768 data sheet.
Layout Considerations
Figures 28 and 29 show the AD768-EB ground and power
plane layouts. Figures 35–38 show the schematic diagram, trace
routing, silk screening, and component layout for the AD768 4
layer evaluation board.
Separate ground and power planes have several advantages for
high speed layouts. (For further information outlining these
advantages, see the application note “Design and Layout of a
Video Graphics System for Reduced EMI” [E1309] available
from Analog Devices [(617) 461-3392].) A solid ground plane
can be used if the digital return current can be routed such that
it does not modulate the analog ground plane. If this is not pos-
sible, it may be necessary to split the ground plane in order to
force currents to flow in a controlled direction. T his type of
grounding scheme is shown in the Figure 28. T he ground plane
is separated into analog and digital planes that are joined
together under the AD768. In any case, the AD768 should be
treated as an analog component and a common ground connec-
tion should be made underneath the AD768 despite some pins
being labeled “digital” ground and some as “analog” ground.
A complete parts list for the AD768 evaluation board is given in
T able IV.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD768-EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
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| AD76901 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 500 kSPS PulSAR ADC in MSOP |
| AD7690BCPZ-R2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD7690BCPZRL | 功能描述:IC ADC 18BIT 400KSPS 10-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
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