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參數(shù)資料
| 型號(hào)： | AD767 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | Microprocessor-Compatible 12-Bit D/A Converter(12位μP兼容DAC) |
| 中文描述： | 微處理器兼容的12位D / A轉(zhuǎn)換器（12位微處理器兼容援會(huì)） |
| 文件頁(yè)數(shù)： | 8/8頁(yè) |
| 文件大?。?/td> | 296K |
| 代理商： | AD767 |
AD767
REV. A
–8–
C
P
Figure 9. TMS32020 – AD767 Interface
ADSP-2100 – AD767 INTERFACE
The ADSP-2100 single chip DSP processor may be interfaced
to the AD767 as shown in Figure 10. With a clock frequency of
32 MHz, and instruction execution in a single 125 ns cycle, the
processor will support the AD767 interface with a single wait
state.
Figure 10. ADSP-2100 – AD767 Interface
At the beginning of the data memory access cycle the processor
provides a 14-bit address on the DMA bus. The
DMS
signal is
then asserted enabling a LOW address decode. Valid data is
now placed on the data bus and
DMWR
is issued.
DMWR
is
OR’ed with the LOW address decode to generate the AD767
CS
.
The LOW decoded address is also gated with the
Q
output of a
D flip-flop to hold DMACK (Data Memory Acknowledge)
LOW. This forces the processor into a wait state and extends
the AD767
CS
by 1 clock cycle. The rising edge of CLKOUT
latches
Q
HIGH bringing DMACK HIGH. The cycle is now
complete.
TMS320C25 – AD767 INTERFACE
Figure 11 illustrates the AD767 interface to a TMS320C25
digital signal processor. Due to the high-speed capability of the
processor (40 MHz), a single wait state is required and is easily
generated using MSC. A 20 MHz TMS320C25 however, does
not require wait states and should be interfaced using the circuit
shown in Figure 9.
Figure 11. TMS320C25 – AD767 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Ceramic (Suffix D)
24-Pin Plastic (Suffix N)
28-Pin PLCC (Suffix P)
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