參數(shù)資料
型號: AD7678ASTZ
廠商: Analog Devices Inc
文件頁數(shù): 14/28頁
文件大?。?/td> 0K
描述: IC ADC 18BIT SAR 100KSPS 48-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
位數(shù): 18
采樣率(每秒): 100k
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 26mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 778 (CN2011-ZH PDF)
配用: EVAL-AD7678CB-ND - BOARD EVALUATION FOR AD7678
AD7678
Rev. A | Page 21 of 28
MASTER SERIAL INTERFACE
Internal Clock
The AD7678 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7678 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 33 and Figure 34 show
the detailed timing diagrams of these two modes.
Usually, because the AD7678 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
12
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t14
t20
t15
t16
t22
t23
t29
t28
t18
t19
t21
t30
t25
t24
t26
t27
03084-0-039
Figure 33. Master Serial Data Timing for Reading (Read after Convert)
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參數(shù)描述
AD7678ASTZ 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LQFP48
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