參數(shù)資料
型號(hào)： AD7678ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT SAR W/BUFF 48LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 26mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
配用： EVAL-AD7678CB-ND - BOARD EVALUATION FOR AD7678
AD7678
Rev. A | Page 19 of 28
POWER DISSIPATION VERSUS THROUGHPUT
The AD7678 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows for a signifi-
cant power savings when the conversion rate is reduced, as
shown in Figure 26. This feature makes the AD7678 ideal for
very low power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be
driven close to the power rails (DVDD and DGND), and
OVDD should not exceed DVDD by more than 0.3 V.
SAMPLING RATE (SPS)
POW
E
R
D
ISSIPA
TION
(
m
W
)
100000
10000
1000
100
10
1
0.1
100k
10k
1k
100
1
10
PDBUF HIGH
03084-0-032
Figure 26. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 27 shows the detailed timing diagrams of the conversion
process. The AD7678 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the
conversion is complete. The CNVST signal operates
independently of the CS and RD signals.
CNVST
t1
t2
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
t7
t8
BUSY
t4
t3
t5
t6
03084-0-033
Figure 27. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
For other applications, conversions can be automatically
initiated. If CNVST is held low when BUSY is low, the AD7678
controls the acquisition phase and then automatically initiates a
new conversion. By keeping CNVST low, the AD7678 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7678 could sometimes
run slightly faster than the guaranteed limits of 100 kSPS.
t9
RESET
DATA
BUS
BUSY
CNVST
t8
03084-0-034
Figure 28. RESET Timing
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AD7678ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 18BIT PARALLEL/SERL 48LQFP - Tape and Reel
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AD7678ASTZ 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LQFP48
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