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參數(shù)資料
| 型號(hào)： | AD7675ACPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SAR 100KSPS 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7675CBZ-ND - BOARD EVALUATION FOR AD7675 |
REV. A
AD7675
–13–
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference which directly affects the full-scale
accuracy if this parameter matters. For instance, a
±15 ppm/°C
tempco of the reference changes the full scale by
±1 LSB/°C.
VREF , as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of VREF, this would essentially increase the
range to make it a
± 3 V input range with an AVDD above
4.85 V. The theoretical improvement as a result of this increase
in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is
approximately 1 dB. The AD780 can be selected with a 3 V
reference voltage.
Power Supply
The AD7675 uses three sets of power supply pins: an analog
5V supply AVDD, a digital 5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD
supply allows direct interface with any logic working between
2.7 V and DVDD + 0.3 V. To reduce the number of supplies
needed, the digital core (DVDD) can be supplied through a
simple RC filter from the analog supply as shown in
Figure 5. The AD7675 is independent of power supply
sequencing once OVDD does not exceed DVDD by more than
0.3 V, and thus free from supply voltage induced latchup.
Additionally, it is very insensitive to power supply variations
over a wide frequency range as shown in Figure 9.
FREQUENCY – Hz
75
PSRR
–
dB
35
65
10k
10M
1k
1M
55
100k
45
70
60
50
40
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
The AD7675 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power saving when the conversion rate is reduced as shown in
Figure 10. This feature makes the AD7675 ideal for very low
power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
SAMPLING RATE – SPS
PO
WER
DISSIP
A
TION
–
W
0.1
10k
100
100k
10
10k
100
1k
1
100k
1k
10
1M
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7675 is controlled by the signal
CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST signal operates independently of
CS and RD signals.
CNVST
t1
t2
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
t7
t8
BUSY
t4
t3
t5
t6
Figure 11. Basic Conversion Timing
For true sampling applications, the recommended operation of
the
CNVST signal is as follows:
CNVST must be held high from the previous falling edge of
BUSY, and during a minimum delay corresponding to the
acquisition time t8; then, when CNVST is brought low, a
conversion is initiated and BUSY signal goes high until the
completion of the conversion. Although
CNVST is a digital
signal, it should be designed with this special care with fast,
clean edges and levels, with minimum overshoot and under-
shoot or ringing.
For applications where the SNR is critical, the
CNVST signal should
have a very low jitter. Some solutions to achieve that are to use a
dedicated oscillator for
CNVST generation or, at least, to clock
it with a high frequency low jitter clock, as shown in Figure 5.
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參數(shù)描述 |
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| AD7675AST | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:100 KSPS 16-BIT DIFFERENTIAL ADC - Tape and Reel 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD7675ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 16BIT PARALLEL/SERL 48LQFP - Tape and Reel |
| AD7675ASTZ | 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7675ASTZRL | 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7676 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit +-1 LSB INL, 500 kSPS, Differential ADC |
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