V
參數(shù)資料
型號: AD766JN
廠商: Analog Devices Inc
文件頁數(shù): 2/8頁
文件大?。?/td> 0K
描述: IC DAC 16BIT W/VREF 16-DIP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 25
系列: DACPORT®
設(shè)置時間: 1.5µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
輸出數(shù)目和類型: 2 電流,雙極;2 電壓,雙極
采樣率(每秒): 390k
REV. A
–2–
AD766–SPECIFICATIONS
AD766J
AD766A
Parameter
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
16
Bits
DIGITAL INPUTS
VIH
2.0
+VL
2.0
+VL
V
VIL
0.8
V
IIH, VIH = VL
1.0
A
IIL, VIL = 0.4
–10
A
SERIAL PORT TIMING
Serial Clock Period (tCLK)
95
115
ns
Serial Clock HI (tHI)30
30
ns
Serial Clock LO (tLO)30
70
ns
Data Valid (tDATA)40
40
ns
Data Setup (tS)15
20
ns
Data Hold (tH)15
20
ns
Clock-to-Latch-Enable (tCTLE)
80
100
ns
Latch-Enable-to-Clock (tLETC)15
15
ns
Latch Enable HI (tLEHI)40
40
ns
Latch Enable LO (tLELO)40
80
ns
ACCURACY
1
Gain Error
±2.0
% of FSR
Gain Drift
±25
ppm of FSR/
°C
Midscale Output Voltage Error
±30
mV
Bipolar Zero Drift
±4
ppm of FSR/
°C
Differential Linearity Error
±0.001
% of FSR
Monotonicity
15
Bits
TOTAL HARMONIC DISTORTION
FOU T = 1037 Hz
1
0 dB
–88
–81
–88
–81
dB
–20 dB
–75
–65
–75
–65
dB
–60 dB
–37
–27
–37
–27
dB
FOUT = 49.07 kHz
2
0 dB
–77
–72
–77
–72
dB
–20 dB
–69
–66
–69
–66
dB
–60 dB
–25
–21
–25
–21
dB
SIGNAL-TO-NOISE RATIO
3
20 Hz to 20 kHz (FOUT = 1037 Hz)
1
94
102
94
102
dB
20 kHz to 250 kHz (FOUT = 49.07 kHz)
2
79
83
79
83
dB
SETTLING TIME (to
± 0.0015% of FSR)
Voltage Output
1
6 V Step
1.5
s
1 LSB Step
1.0
s
Slew Rate
9
V/
s
Current Output
1 mA Step 10
to 100 Load
350
ns
1 k
Load
350
ns
OUTPUT
Voltage Output Configuration
1
Bipolar Range
±2.88
±3.0
±3.12
±2.88
±3.0
±3.12
V
Output Current
±8.0
mA
Output Impedance
0.1
Short Circuit Duration
Indefinite to Common
Current Output Configuration
Bipolar Range
±0.7
±1.0
±1.3
±0.7
±1.0
±1.3
mA
Output Impedance (
±30%)
1.7
k
POWER SUPPLY
Voltage: +VL and +VS
4.75
13.2
4.75
13.2
V
Voltage: –VL and –VS
–13.2
–4.75
–13.2
–4.75
V
Current Case 1
1: V
S and VL = +5 V
+I
12.0
15.0
12.0
15.0
mA
Current Case 1
1: –V
S and –VL = –5 V
–I
–12.0
–15.0
–12.0
–15.0
mA
Current Case 2:
1 V
S and VL = +12 V
+I
10.5
mA
Current Case 2:
1 –V
S and –VL = –12 V
–I
–14
mA
Current Case 3
4: V
S and VL = +5 V
+I
12
mA
Current Case 2:1 –VS and –VL = –12 V
–I
–14
mA
Power Dissipation: VS and VL = ± 5 V
1
120
150
120
150
mW
Power Dissipation: VS and VL = ± 12 V
300
mW
Power Dissipation: VS and VL = +5 V,
Power Dissipation: –VS and –VL = –12 V
4
225
mW
(TMIN to TMAX,
5 V supplies, FS = 500 kSPS unless otherwise noted. No deglitchers or
MSB trimming is used.)
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