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參數(shù)資料
| 型號： | AD7665 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | TV 8C 8#20 PIN PLUG |
| 中文描述： | 16位，570 kSPS的的CMOS模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD7665 |
REV. 0
AD7665
–20–
CNVST
SDOUT
SCLK
D1
D0
X
D15
D14
D13
1
2
3
14
15
16
t
3
t
35
t
36
t
37
t
31
t
32
t
16
BUSY
INVSCLK = 0
CS
,
RD
EXT/
INT
= 1
RD
= 0
Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
External Clock Data Read During Conversion
Figure 21 shows the detailed timing diagrams of this method.
During a conversion, while both
CS
and
RD
are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both rising and
falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no “daisy chain” fea-
ture in this mode and RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of, at least 25 MHz, when impulse mode is
used, 40 MHz when normal or warp mode is used, is recom-
mended to ensure that all the bits are read during the first half
of the conversion phase. It is also possible to begin to read the
data after conversion and continue to read the last bits even after
a new conversion has been initiated. That allows the use of a slower
clock speed like 10 MHz in impulse mode, 12 MHz in normal
mode and 15 MHz in warp mode.
MICROPROCESSOR INTERFACING
The AD7665 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal process-
ing applications interfacing to a digital signal processor. The
AD7665 is designed to interface either with a parallel 8-bit or
16-bit wide interface or with a general purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7665 to prevent digital noise from coupling
into the ADC. The following sections illustrate the use of the
AD7665 with an SPI equipped microcontroller, the ADSP-
21065L and ADSP-218x signal processors.
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7665 and
an SPI-equipped microcontroller like the MC68HC11. To
accommodate the slower speed of the microcontroller, the
AD7665 acts as a slave device and data must be read after con-
version. This mode also allows the “daisy chain” feature. The
convert command could be initiated in response to an internal
timer interrupt. The reading of output data, one byte at a time,
if necessary, could be initiated in response to the end-of-conver-
sion signal (BUSY going low) using an interrupt line of the
microcontroller. The Serial Peripheral Interface (SPI) on the
MC68HC11 is configured for master mode (MSTR) = 1, Clock
Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI
interrupt enable (SPIE) = 1 by writing to the SPI Control Regis-
ter (SPCR). The IRQ is configured for edge-sensitive-only
operation (IRQE = 1 in OPTION register).
IRQ
MC68HC11
*
CNVST
AD7665
*
BUSY
CS
RD
MISO/SDI
SCK
I/O PORT
SDOUT
SCLK
INVSCLK
EXT/
INT
DVDD
*
ADDITIONAL PINS OMITTED FOR CLARITY
SER/
PAR
Figure 22. Interfacing the AD7665 to SPI Interface
ADSP-21065L in Master Serial Interface
As shown in Figure 23, the AD7665 can be interfaced to the
ADSP-21065L using the serial interface in master mode without
any glue logic required. This mode combines the advantages
of reducing the wire connections and the ability to read the
data during or after conversion maximum speed transfer
(DIVSCLK[0:1] both low).
The AD7665 is configured for the internal clock mode (EXT/
INT
low) and acts, therefore, as the master device. The convert
command can be generated by either an external low jitter oscil-
lator or, as shown, by a FLAG output of the ADSP-21065L or
by a frame output TFS of one serial port of the ADSP-21065L
which can be used like a timer. The serial port on the ADSP-
21065L is configured for external clock (IRFS = 0), rising edge
active (CKRE = 1), external late framed sync signals (IRFS = 0,
LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial
port of the ADSP-21065L is configured by writing to its receive
control register (SRCTL)—see
ADSP-2106x SHARC User’s
Manual
. Because the serial port within the ADSP-21065L will
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