參數(shù)資料
型號(hào)： AD7664ASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/24頁(yè)
文件大小： 0K
描述： IC ADC 16BIT UNIPOLAR 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 570k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 115mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)偽差分，單極
配用： EVAL-AD7664CBZ-ND - BOARD EVALUATION FOR AD7664
REV. E
AD7664
–5–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1
AGND
P
Analog Power Ground Pin.
2
AVDD
P
Input Analog Power Pins. Nominally 5 V.
3, 40–42,
NC
No Connect.
44–48
4
DGND
DI
Must Be Tied to the Ground Where DVDD Is Referred.
5OB/
2C
DI
Straight Binary/Binary Twos Complement. When OB/
2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a twos complement output from
its internal shift register.
6
WARP
DI
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
7
IMPULSE
DI
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
9–12
D[0:3]
DO
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/
PAR.
13
D4
DI/O
When SER/
PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/
INT
When SER/
PAR is HIGH, this input, part of the Serial Port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/
INT tied LOW, the internal
clock is selected on the SCLK output. With EXT/
INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
14
D5
DI/O
When SER/
PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC
When SER/
PAR is HIGH, this input, part of the Serial Port, is used to select the active state
of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
15
D6
DI/O
When SER/
PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/
PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Mode.
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
DGND
OB/
2C
WARP
IMPULSE
NC = NO CONNECT
SER/
PAR
D0
D1
D2
BUSY
D15
D14
D13
AD7664
D3
D12
D4/EXT/
INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
NC
IN
NC
INGND
REFGND
REF
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