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參數(shù)資料
| 型號： | AD7664 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| 中文描述： | 16位，570 kSPS的的CMOS模數(shù)轉換器 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 392K |
| 代理商： | AD7664 |
REV. 0
AD7664
–10–
CIRCUIT INFORMATION
The AD7664 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7664 fea-
tures different modes to optimize performances according to
the applications.
In warp mode, the AD7664 is capable of converting 570,000
samples per second (570 kSPS).
The AD7664 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7664 can be operated from a single 5 V supply and
be interfaced to either 5 V or 3 V digital logic. It is housed in
a 48-lead LQFP package that saves space and allows flexible con-
figurations as either serial or parallel interface. The AD7664 is a
pin-to-pin compatible upgrade of the AD7660.
CONVERTER OPERATION
The AD7664 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected
to a “dummy” capacitor of the same value as the capacitive
DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW
A
. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the
CNVST
input goes low, a conversion phase is
initiated. When the conversion phase begins, SW
A
and SW
B
are opened first. The capacitor array and the “dummy” capaci-
tor are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
IN and INGND captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND or REF, the comparator input varies by
binary-weighted voltage steps (V
REF
/2, V
REF
/4, . . . V
REF
/65536).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and brings BUSY output low.
SW
A
COMP
SW
B
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C
4C
2C
C
C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
Modes of Operation
The AD7664 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 570 kSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7664
ideal for applications where both high accuracy and fast sample
rate are required.
The normal mode is the fastest mode (500 kSPS ) without any
limitation about the time between conversions. This mode makes
the AD7664 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 21
μ
W. This feature
makes the AD7664 ideal for battery-powered applications.
Transfer Functions
Using the OB/
2C
digital input, the AD7664 offers two output
codings: straight binary and two’s complement. The LSB size is
V
REF
/65536, which is about 38.15
μ
V. The ideal transfer charac-
teristic for the AD7664 is shown in Figure 4 and Table I.
000...000
000...001
000...010
111...101
111...110
111...111
A
–
ANALOG INPUT
V
REF
–
1.5 LSB
V
REF
–
1 LSB
1 LSB
0V
0.5 LSB
1 LSB = V
REF
/65536
Figure 4. ADC Ideal Transfer Function
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7664ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:ADC SGL SAR 570KSPS 16BIT PARALLEL/SERL 48LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述:16-BIT, 500KSPS CMOS ADC - Bulk |
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| AD7664ACPZ | 功能描述:IC ADC 16BIT UNIPOLAR 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:PulSAR® 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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| AD7664AST | 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT, 500KSPS CMOS ADC - Tape and Reel 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
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