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參數(shù)資料
| 型號： | AD7660ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 218K |
| 代理商： | AD7660ASTRL |
REV. 0
–3–
AD7660
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15
μ
V.
2
Typical rms noise at worst-case transitions and temperatures.
3
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input F
S
. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
5
Tested in parallel reading mode.
6
With all digital inputs forced to DVDD or DGND respectively.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
t
1
t
2
t
3
t
4
5
10
ns
μ
s
ns
μ
s
15
2
t
5
t
6
t
7
t
8
t
9
2
ns
ns
μ
s
μ
s
ns
10
2
8
10
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t
10
t
11
t
12
t
13
2
μ
s
ns
ns
ns
45
40
50
5
Refer to Figures 16, and 17 (Master Serial Interface Modes)
1
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH (INVSCLK Low)
2
Internal SCLK LOW (INVSCLK Low)
2
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
CNVST
LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
10
10
10
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
0.5
4
40
30
9.5
4.5
3
3
75
10
10
10
3.2
ns
ns
ns
μ
s
μ
s
ns
1.5
50
Refer to Figures 18 and 20 (Slave Serial Interface Modes)
1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
16
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
(–40 C to +85 C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
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