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| 型號(hào)： | AD7658BSTZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC |
| 中文描述： | 6-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 308K |
| 代理商： | AD7658BSTZ-REEL |
Preliminary Technical Data
AD7658/AD7657/AD7656
devices in Daisy Chain Mode.
Rev. PrI | Page 21 of 25
The CS falling edge is used to frame the serial transfer from the
AD7658/AD7657/AD7656 devices, take the bus out of three-
state and clock out the MSB of the first conversion result. In the
example shown all twelve ADC channels were simultaneously
sampled. Two DOUT line are used to read the conversion
results in this example. CS frames a 96 SCLK transfer. During
the first 48 SCLK the conversion data is transferred from Device
#2 to Device #1. DOUT A on device #2 transfers conversion
data from V1, V2 and V5 into DCINA in device #1. DOUT B on
device #2 transfers conversion results from V3, V4 and V6 to
DCIN B in device #1. During the first 48 SCLK device #1
transfers data into the digital host, DOUTA on device #1
transfers conversion data from V1, V2 and V5. DOUTB on
device #1 transfers conversion data from V3, V4 and V6.
During the last 48 SCLKs device #2 will clock out zeros, device
#1 will shift the data it clocked in from device #2 during the
first 48 SCLKs into the digital host. This example could also
have been implemented using 3 x 32 SCLK individually framed
SCLK transfers or 6 x 16 SCLK individually framed SCLK
transfers provided DCEN remained high during the transfers.
Figure 14 shows the timing if two AD7656 were configured in
Daisy chain mode but operating with three DOUT lines. Again
assuming a simultaneous sampling of all 12 inputs occurred.
During the read operation the CS frames a 64 SCLK transfer.
During the first 32 SCLKs of this transfer the conversion results
from Device #1 are clocked into the digital host and the
conversion results from device #2 are clocked into device #1.
During the last 32 SCLKs of the transfer the conversion results
from device #2 are clocked out of device #1 and into the digital
host. Device #2 will clock out zeros.
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Figure 12. Daisy-Chain Configuration
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Figure 13. Daisy-Chain Serial Interface Timing with 2 DOUT lines
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