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參數(shù)資料
| 型號： | AD7655ACPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 684K |
| 代理商： | AD7655ACPRL |
REV. 0
–16–
AD7655
MASTER SERIAL INTERFACE
Internal Clock
The AD7655 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT
pin is held low. The AD7655
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired.
The output data is valid on both the rising and falling edge of
the data clock. Depending on RDC/SDIN input, the data can be
read after each conversion or during the following conversion.
Figures 15 and 16 show the detailed timing diagrams of these
two modes.
Usually, because the AD7655 is used with a fast throughput, the
mode master, read during conversion is the most recommended
serial mode when it can be used.
In read after conversion mode, it should be noted that unlike in
other modes, the signal BUSY returns low after the 32 data bits
are pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width. One advantage of this mode is
t
3
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
1
2
16
30
31
32
CH A
D15
CH A
D14
t
30
CH B
D2
CH B
D1
CH B D0
X
EXT/
INT
= 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
21
t
27
t
22
t
23
t
29
t
36
t
25
t
26
t
28
t
37
t
32
t
31
t
33
t
34
A/
B
= 1
EOC
t
12
t
13
17
t
35
Figure 15. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT
= 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
24
t
21
t
26
t
27
t
28
t
31
t
33
t
32
t
34
t
30
t
29
t
23
t
22
CH A
D15
X
1
2
16
1
2
t
25
BUSY
SYNC
SCLK
SDOUT
CS
,
RD
CNVST
16
CH B
D15
CH A D0
CH A
D14
CH B
D14
CH B D0
A/
B
= 1
EOC
t
10
t
11
t
13
t
12
Figure 16. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
相關(guān)PDF資料 |
PDF描述 |
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| AD7655AST | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| AD7655ASTRL | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| AD7660 | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| AD7660AST | 16-Bit, 100 kSPS CMOS ADC |
| AD7660ASTRL | 16-Bit, 100 kSPS CMOS ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7655ACPZ | 功能描述:IC ADC 16BIT 4CH 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7655ACPZRL | 功能描述:IC ADC 16BIT 4CHAN 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7655AST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LQFP48 |
| AD7655ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7655ASTZ | 功能描述:IC ADC 16BIT 1MSPS QUAD 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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