參數(shù)資料
型號(hào)： AD7650ASTZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 570KSPS 48LQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
采樣率（每秒）： 570k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 77mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)偽差分，單極
配用： EVAL-AD7650CBZ-ND - BOARD EVALUATION FOR AD7650
REV. 0
–13–
AD7650
POWER DISSIPATION VS. THROUGHPUT
Operating currents are very low during the acquisition phase,
which allows a significant power saving when the conversion
rate is reduced as shown in Figure 7. This power saving depends
on the mode used. In impulse mode, the AD7650 automatically
reduces its power consumption at the end of each conversion
phase. This feature makes the AD7650 ideal for very low power
battery applications. It should be noted that the digital interface
remains active even during the acquisition phase. To reduce the
operating digital supply currents even further, the digital inputs
need to be driven close to the power supply rails (i.e., DVDD or
DGND for all inputs except EXT/
INT, INVSYNC, INVSCLK,
RDC/SDIN, and OVDD or OGND for these last four inputs).
100k
0.1
PO
WER
DISSIP
A
TION
–
W
SAMPLING RATE – SPS
100k
1k
10
1
100
10k
1M
10k
1k
100
10
1
0.1
WARP/NORMAL
IMPULSE
Figure 7. Power Dissipation vs. Sampling Rate
CONVERSION CONTROL
Figure 8 shows the detailed timing diagrams of the conversion
process. The AD7650 is controlled by the signal
CNVST which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST signal operates independently of
CS and RD signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 8. Basic Conversion Timing
In impulse mode, conversions can be automatically initiated.
If
CNVST is held low when BUSY is low, the AD7650 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping
CNVST low, the AD7650 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7650 could sometimes
run slightly faster then the guaranteed limits in the impulse mode
of 444 kSPS. This feature does not exist in warp or normal modes.
t9
t8
RESET
DATA
BUSY
CNVST
Figure 9. RESET Timing
Although
CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
It is a good thing to shield the
CNVST trace with ground and
also to add a low value serial resistor (i.e., 50 V) termination
close to the output of the component that drives this line.
For applications where the SNR is critical,
CNVST signal should
have a very low jitter. Some solutions to achieve that is to use a
dedicated oscillator for
CNVST generation or, at least, to clock
it with a high-frequency low-jitter clock as shown in Figure 5.
DIGITAL INTERFACE
The AD7650 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7650 digital interface also accommodates both 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7650 to
the host system interface digital supply. Finally, by using the
OB/
2C input pin, both two’s complement or straight binary
coding can be used.
The two signals
CS and RD control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually,
CS allows the selection of each AD7650 in
multicircuits applications and is held low in a single AD7650
design.
RD is generally used to enable the conversion result on
the data bus.
t1
t3
t4
t11
CNVST
BUSY
DATA
BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 10. Master Parallel Data Timing for Reading
(Continuous Read)
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