- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373911 > AD7641BSTZRL (ANALOG DEVICES INC) 18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC PDF資料下載
參數(shù)資料
| 型號： | AD7641BSTZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LEAD FREE, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 192K |
| 代理商： | AD7641BSTZRL |
Preliminary Technical Data
AD7631/AD7634
Parameter
Rev. PrC | Page 7 of 14
Symbol
Min
Typ
Max
Unit
BUSY High in Master Serial Read after Convert
4
CNVST Low to SYNC Asserted Delay (all Modes)
AD7631
AD7634 (Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
1
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
3
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
4
In serial master read during convert mode. See
Error! Reference source not found.
for serial master read after convert mode timing specifications.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum (Warp mode)
BUSY High Width Maximum (Normal mode)
BUSY High Width Maximum (Impulse mode)
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
1
5
5
12.5
5
5
See
Table 4
TBD
TBD
25
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
t
18
t
19
t
19
t
20
t
21
t
22
t
23
t
24
t
28
t
28
t
28
0
0
3
25
40
12
7
4
2
3
1.75
2
2.25
0
1
17
60
80
22
21
18
4
60
2.5
2.75
3
1
0
17
120
160
50
49
18
30
140
4
4.25
4.5
1
1
17
240
320
100
99
18
89
300
7
7.25
7.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7641 | 18-Bit, 2 MSPS SAR ADC |
| AD7641ACP | 18-Bit, 2 MSPS SAR ADC |
| AD7641ACPRL | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7641AST | 18-Bit, 2 MSPS SAR ADC |
| AD7641ASTRL | 18-Bit, 2 MSPS SAR ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7641XST | 制造商:Analog Devices 功能描述: |
| AD7641XST-U3 | 制造商:Analog Devices 功能描述: |
| AD7643 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
| AD7643BCPZ | 功能描述:IC ADC 18BIT DIFF W/REF 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7643BCPZRL | 功能描述:IC ADC 18BIT DIFF W/REF 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。