參數(shù)資料
型號(hào)： AD7634BSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT DIFF BIPO 48-LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 670k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 225mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
Data Sheet
AD7634
Rev. B | Page 25 of 32
18-Bit Interface (Master or Slave)
The 18-bit interface is selected by setting MODE[1:0] = 0. In
this mode, the data output is straight binary.
16-Bit and 8-Bit Interface (Master or Slave)
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, Pin A0 and Pin A1 allow a glueless interface to a
16- or 8-bit bus, as shown in Figure 40 (refer to Table 7 for
more details). By connecting Pin A0 and Pin A1 to an address
line(s), the data can be read in two words for a 16-bit interface,
or three bytes for an 8-bit interface. This interface can be used
in both master and slave parallel reading modes.
CS, RD
A1
D[17:2]
HI-Z
HIGH
WORD
LOW
WORD
HI-Z
t12
t13
HIGH
BYTE
A0
MID
BYTE
LOW
BYTE
D[17:10]
t12
HI-Z
t12
0
64
06
-04
0
Figure 40. 8-Bit and16-Bit Parallel Interface
SERIAL INTERFACE
The AD7634 is configured to use the serial interface
when MODE[1:0]= 3. The AD7634 has a serial interface
(SPI-compatible) multiplexed on the data pins D[17:4].
Data Interface
The AD7634 outputs 18 bits of data, MSB first, on the SDOUT pin.
This data is synchronized with the 18 clock pulses provided on
the SDCLK pin. The output data is valid on both the rising and
falling edge of the data clock.
Serial Configuration Interface
The AD7634 can be configured through the serial configuration
register only in serial mode as the serial configuration pins are
also multiplexed on the data pins D[17:14]. See the Hardware
for more information.
MASTER SERIAL INTERFACE
The pins multiplexed on D[12:4] and used for master serial
interface are: DIVSCLK[1:0], EXT/INT, INVSYNC, INVSCLK,
RDC, SDOUT, SDCLK, and SYNC.
Internal Clock (MODE[1:0] = 3, EXT/INT = Low)
The AD7634 is configured to generate and provide the serial
data clock, SDCLK, when the EXT/INT pin is held low. The
AD7634 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK and the SYNC signals
can be inverted, if desired, using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data
can be read during the following conversion or after each con-
version. Figure 41 and Figure 42 show detailed timing diagrams
of the following two modes.
Read During Convert (RDC = High)
Setting RDC = high allows the master read (previous conver-
sion result) during conversion mode. Usually, because the
AD7634 is used with a fast throughput, this mode is the most
recommended serial mode. In this mode, the serial clock and data
switch on and off at appropriate instances, minimizing potential
feedthrough between digital activity and critical conversion
decisions. In this mode, the SDCLK period changes because the
LSBs require more time to settle and the SDCLK is derived
from the SAR conversion cycle. In this mode, the AD7634
generates a discontinuous SDCLK of two different periods
and the host should use an SPI interface.
Read After Covert (RDC = Low, DIVSCLK[1:0] = 0 to 3)
Setting RDC = low allows the read after conversion mode. Unlike
the other serial modes, the BUSY signal returns low after the 18
data bits are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width (See Table 4 for BUSY timing
specifications). The DIVSCLK[1:0] inputs control the SDCLK
period and SDOUT data rate. As a result, the maximum through-
put cannot be achieved in this mode. In this mode, the AD7634
also generates a discontinuous SDCLK; however, a fixed period and
hosts supporting both SPI and serial ports can also be used.
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