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參數(shù)資料
| 型號(hào)： | AD7626BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 10MSPS DIFF 32LFCSP |
| 設(shè)計(jì)資源： | Single-Ended-to-Differential High Speed Drive Circuit for 16-Bit, 10 MSPS AD7626 ADC (CN0105) |
| 特色產(chǎn)品： | AD7626 PulSAR Differential ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 170mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，雙極 |
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Data Sheet
AD7626
Rev. B | Page 23 of 28
Self-Clocked Mode
The digital operation of the AD7626 in self-clocked interface
mode is shown in Figure 42. This interface mode reduces the
number of traces between the ADC and the digital host to two
LVDS pairs (CLK± and D±) or to a single pair if sharing a
common CLK±. Multiple AD7626 devices can share a common
CLK± signal. This can be useful in reducing the number of
LVDS connections to the digital host.
When the self-clocked interface mode is used, each ADC
data-word is preceded by a 010 sequence. The first zero is
automatically on D± once tMSB has elapsed. The 2-bit header
is then clocked out by the first two CLK± falling edges. This
header is used to synchronize D± of each conversion in the
digital host because, in this mode, there is no data clock output
synchronous to the data (D±) to allow the digital host to
acquire the data output.
Synchronization of the D± data to the digital host’s acquisition
clock is accomplished by using one state machine per AD7626
device. For example, using a state machine that runs at the
same speed as CLK± incorporates three phases of this clock
frequency (120 apart). Each phase acquires the data D± as
output by the ADC.
The AD7626 data captured on each phase of the state
machine clock is then compared. The location of the 1 in
the header in each set of data acquired allows the user to
choose the state machine clock phase that occurs during
the data valid window of D±.
The self-clocked mode data capture method allows the digital
host to adapt its result capture timing to accommodate
variations in propagation delay through any AD7626.For
example, where data is captured from multiple AD7626s
sharing a common input clock.
Conversions are initiated by a CNV± pulse. The CNV± pulse
must be returned low (tCNVH maximum) for valid operation.
After a conversion begins, it continues until completion.
Additional CNV± pulses are ignored during the conversion
phase. After the time, tMSB, elapses, the host begins to burst
the CLK± signal to the AD7626. All 18 CLK± pulses are to be
applied in the time window framed by tMSB and the subsequent
tCLKL. The required 18 CLK± pulses must finish before tCLKL
(referenced to the next conversion phase) elapses. Otherwise,
the data is lost because it is overwritten by the next conversion
result.
Set CLK± to idle high between bursts of 18 CLK± pulses. The
header bit and conversion data of the next ADC result are
output on subsequent falling edges of CLK± during the next
burst of the CLK± signal.
CLK+
18
17
1
4
2
1
23
tCLKL
D+
D–
CLK–
D0
N – 1
D1
N – 1
ACQUISITION
tCLKD
tCLK
tMSB
18
17
3
D15
N
D14
N
D1
N
0
1
D0
N
D15
N + 1
0
1
tCYC
CNV+
tCNVH
SAMPLE N
SAMPLE N + 1
CNV–
07
64
8-
1
04
Figure 42. Self-Clocked Interface Mode Timing Diagram
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| AD7626BCPZ-RL7 | 功能描述:IC ADC 16BIT 10MSPS DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7628 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS Dual 8-Bit Buffered Multiplying DAC |
| AD7628BFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7628BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7628BQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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