參數(shù)資料
型號： AD7621ASTRL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝： MO-026-BBC, LQFP-48
文件頁數(shù)： 16/26頁
文件大?。?/td> 265K
代理商： AD7621ASTRL
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–16–
100nF
10 F
100nF
10 F
AVDD
REFBUFIN
10 F
100nF
AGND
DGND
DVDD
OVDD
OGND
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
10
D
CLOCK
AD7621
C/ P/DSP
SERIAL
PORT
DIGITAL SUPPLY
(2.5V OR 3.3V)
ANALOG
SUPPLY
(2.5V)
DVDD
OB/2C
note 6
DVDD
IN+
IN-
ANALOG INPUT-
C
C
1.2nF
note 3
15
note 5
50
note 4
AD8021
NOTES :
Note 1 : See Voltage Reference Input Section.
Note 2 : CREF is 10 F ceramic capacitor or low esr tantalum. Ceramic size 1206 Panasonic ECJ-3xB0J106 is recommended. See Voltage Reference Input Section.
Note 3 : The AD8021 is recommended. See Driver Amplifier Choice Section.
Note 4 : See Analog Inputs Section.
Note 5 : Option. See Power Supply Section.
Note 6 : Optional Low jitter CNVST. See Conversion Control Section.
ANALOG INPUT+
C
C
1.2nF
note 3
15
note 4
AD8021
MODE1
MODE0
REFGND
C
REF
REF
10 F
note 2
PDBUF
PDREF
C
REF
100nF
note 1
Transfer Functions
Using the OB/
2C
digital input, the AD7621 offers two
output codings: straight binary and two’s complement.
The ideal transfer characteristic for the AD7621 is shown
in Figure 4 and Table III.
000...000
000...001
000...010
111...101
111...110
111...111
A
ANALOG INPUT
+FS-1.5 LSB
+FS-1 LSB
-FS+1 LSB
-FS
-FS+0.5 LSB
Figure 4. ADC Ideal Transfer Function
Table III. Output Codes and Ideal Input Voltages
Digital Output Code
Hexa
Straight
Binary
Analog
Input
V
REF
= 2.048V
Two’s
Comple-
ment
D
escription
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB 75.684μV
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
2.047924 V
2.047849 V
3FFFF
1
3FFFE
20001
20000
1FFFF
00001
00000
2
1FFFF
1
1FFE
00001
00000
3FFFF
20001
20000
2
0 V
-75.684μV
-2.047924 V
-2.048 V
NOTES
1
This is also the code for overrange analog input (V
IN+
– V
IN-
above
V
REF
– V
REFGND
).
2
This is also the code for underrange analog input (V
IN+
– V
IN-
below
-V
REF
+ V
REFGND
).
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