參數(shù)資料
型號： AD7610BSTZ-RL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝： LEAD FREE, MO-026BBC, LQFP-48
文件頁數(shù)： 10/32頁
文件大小： 591K
代理商： AD7610BSTZ-RL
AD7610
Pin No.
27
Rev. 0 | Page 10 of 32
Mnemonic
D14 or
SCCLK
Type
1
DI/O
Description
In parallel mode, this output is used as Bit 14 of the parallel port data output bus.
Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is
used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state
of the INVSCLK pin. See the
Software Configuration
section.
In parallel mode, this output is used as Bit 15 of the parallel port data output bus.
Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input enables the serial configuration port. See the
Software Configuration
section.
Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low,
RDC = low) the busy time changes according to
Table 4
.
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range
BIPOLAR
TEN
0 V to 5 V
Low
Low
0 V to 10 V
Low
High
±5 V
High
Low
±10 V
High
High
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also
used to gate the external clock in slave serial mode (not used for serial programmable port).
Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET
resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register. See the
Digital
Interface
section. If not used, this pin can be tied to OGND.
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions
are inhibited after the current one is completed. The digital interface remains active during power down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates
a conversion.
Input Range Select. See description for Pin 30.
Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V
on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the
internal reference and buffer. See the
Reference Decoupling
section.
Reference Input Analog Ground. Connected to analog ground plane.
Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
High Voltage Positive Supply. Normally +7 V to +15 V.
High Voltage Negative Supply. Normally 0 V to 15 V (0 V in unipolar ranges).
Analog Input. Referenced to IN.
Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF =
low). See the
Temperature Sensor
section.
Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,
PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the
Voltage Reference Input
section.
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
28
D15 or
SCCS
DI/O
29
BUSY
DO
30
TEN
DI
2
31
32
RD
CS
DI
DI
33
RESET
DI
34
PD
DI
2
35
CNVST
DI
36
37
BIPOLAR
REF
DI
2
AI/O
38
39
40
41
43
45
REFGND
IN
VCC
VEE
IN+
TEMP
AI
AI
P
P
AI
AO
46
REFBUFIN
AI
47
PDREF
DI
48
PDBUF
DI
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2
In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration
section and
Software Configuration
section.
相關(guān)PDF資料
PDF描述
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