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參數(shù)資料
| 型號： | AD760 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16/18-Bit Self-Calibrating Serial/Byte DACPORT(16/18位自校準單片D/A轉(zhuǎn)換器) |
| 中文描述： | 16/18-Bit自校準串行/字節(jié)DACPORT（16/18位自校準單片的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 333K |
| 代理商： | AD760 |
AD760
REV. A
–11–
The HC11 generates the requisite 8 clock pulses with data valid
on the rising edges. After the most significant byte is transmit-
ted, the least significant byte (LSBY) is loaded from memory
and transmitted in a similar fashion. To complete the transfer,
the LDAC pin is driven high latching the complete 16-bit word
into the AD760.
I
NIT
LDAA
#$2F
;
SS
= 1; SCK = 0; MOSI = I
STAA
PORTD
;SEND TO SPI OUTPUTS
LDAA
#$38
;SS
, SCK,MOSI = OUTPUTS
STAA
DDRD
;SEND DATA DIRECTION INFO
LDAA
#$50
;DABL INTRPTS,SPI IS MASTER & ON
STAA
SPCR
;CPOL=0, CPHA=0,1MHZ BAUD RATE
NEXTPT LDAA
MSBY
SENDAT ;JUMP TO DAC OUTPUT ROUTINE
NEXTPT ;INFINITE LOOP
;LOAD ACCUM W/UPPER 8 BITS
BSR
JMP
SENDAT LDY
#$1000
$08,Y,$20 ;DRIVE
SS
(LDAC) LOW
SPDR
;SEND MS-BYTE TO SPI DATA REG
;POINT AT ON-CHIP REGISTERS
BCLR
STAA
WAIT1
LDAA
BPL
LDAA
STAA
SPSR
WAIT1
LSBY
SPDR
;CHECK STATUE OF SPIE
;POLL FOR END OF X-MISSION
;GET LOW 8 BITS FROM MEMORY
;SEND LS-BYTE TO SPI DATA REG
WAIT2
LDAA
BPL
BSET
RTS
SPSR
WAIT2
$08,Y,$20 ;DRIV
SS
HIGH TO LATCH DATA
;CHECK STATUS OF SPIE
;POLL FOR END OF X-MISSION
MOSI
68HC11
SS
S
IN
LDAC
SER
AD760
SCK
CS
Figure 11. AD760 to 68HC11 (SPI) Interface
AD760 TO MICROWIRE INTERFACE
The flexible serial interface of the AD760 is also compatible
with the National Semiconductor MICROWIRE* interface.
The MICROWIRE* interface is used on microcontrollers such
as the COP400 and COP800 series of processors. A generic in-
terface to the MICROWIRE interface is shown in Figure 12.
The G1, SK, and SO pins of the MICROWIRE interface are re-
spectively connected to the LDAC,
CS
and S
IN
pins of the
AD760.
S
IN
LDAC
SER
AD760
SO
SK
G1
MICROWIRE
CS
Figure 12. AD760 to MICROWIRE Interface
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 153 μV
(–96 dB). Therefore, the noise must remain below this level in
*MICROWIRE is a registered trademark of National Semiconductor.
the frequency range of interest. The AD760’s noise spectral
density is shown in Figures 13 and 14. Figure 13 shows the
DAC output noise voltage spectral density for a 20 V span ex-
cluding the reference. This figure shows the l/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/
Hz
.
Figure 14 shows the reference wideband noise to be below
125 nV/
Hz
.
1000
1
1
1M
100
10
10
100k
10k
1k
100
10M
FREQUENCY – Hz
N
Figure 13. DAC Output Noise Voltage Spectral Density
1000
1
1
1M
100
10
10
100k
10k
1k
100
10M
FREQUENCY – Hz
N
Figure 14. Reference Noise Voltage Spectral Density
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 μA current through a 0.5 trace will develop a voltage
drop of 153 μV, which is 1 LSB at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes should also be used, with a single in-
terconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
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