參數(shù)資料
型號(hào)： AD7607BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： IC DAS W/ADC 14BIT 8CH 64LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 14 b
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，并聯(lián)，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 2.3 V ~ 5.25 V，4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤(pán)
Data Sheet
AD7607
Rev. B | Page 23 of 32
CONVERSION CONTROL
Simultaneous Sampling on All Analog Input Channels
The AD7607 allows simultaneous sampling of all analog input
channels. All channels are sampled simultaneously when both
CONVST pins (CONVST A, CONVST B) are tied together. A
single CONVST signal is used to control both CONVST x inputs.
The rising edge of this common CONVST signal initiates
simultaneous sampling on all analog input channels.
The AD7607 contains an on-chip oscillator that is used to
perform the conversions. The conversion time for all ADC
channels is tCONV. The BUSY signal indicates to the user when
conversions are in progress, so when the rising edge of CONVST
is applied, BUSY goes logic high and transitions low at the end
of the entire conversion process. The falling edge of the BUSY
signal is used to place all eight track-and-hold amplifiers back
into track mode. The falling edge of BUSY also indicates that
the new data can now be read from the parallel bus (DB[15:0]),
the DOUTA and DOUTB serial data lines, or the parallel byte bus
(DB[7:0]).
Simultaneously Sampling Two Sets of Channels
The AD7607 also allows the analog input channels to be sampled
simultaneously in two sets. This can be used in power-line
protection and measurement systems to compensate for phase
differences between current and voltage sensors. In a 50 Hz
system, this allows for up to 9° of phase compensation; and in a
60 Hz system, it allows for up to 10° of phase compensation.
This is accomplished by pulsing the two CONVST pins
independently and is possible only if oversampling is not in
use. CONVST A is used to initiate simultaneous sampling of
the first set of channels (V1 to V4), and CONVST B is used
to initiate simultaneous sampling on the second set of analog
input channels (V5 to V8), as illustrated in Figure 40.
On the rising edge of CONVST A, the track-and-hold
amplifiers for the first set of channels are placed into hold
mode. On the rising edge of CONVST B, the track-and-hold
amplifiers for the second set of channels are placed into hold
mode. The conversion process begins when both rising edges
of CONVST x have occurred; therefore, BUSY goes high on the
rising edge of the later CONVST x signal. In Table 3, Time t5
indicates the maximum allowable time between CONVST x
sampling points.
There is no change to the data read process when using two
separate CONVST x signals.
Connect all unused analog input channels to AGND. The results
for any unused channels are still included in the data read because
all channels are always converted.
CONVST A
CONVST B
BUSY
CS/RD
DATA: DB[15:0]
FRSTDATA
V1
V2
V3
V7
V8
t5
tCONV
V1 TO V4 TRACK-AND-HOLD
ENTER HOLD
V5 TO V8 TRACK-AND-HOLD
ENTER HOLD
AD7607 CONVERTS
ON ALL 8 CHANNELS
08096-
040
Figure 40. Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Interface Mode
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AD7608BSTZ 功能描述:IC DAS W/ADC 18BIT 8CH 64LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1
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