參數(shù)資料
型號: AD7606BSTZ-4
廠商: Analog Devices Inc
文件頁數(shù): 18/36頁
文件大?。?/td> 0K
描述: IC DAS W/ADC 16BIT 4CH 64LQFP
設計資源: Layout Considerations for an Expandable Multichannel Simultaneous Sampling Data Acquisition System Based on AD7606 (CN0148)
標準包裝: 1
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 16 b
采樣率(每秒): 200k
數(shù)據(jù)接口: DSP,MICROWIRE?,并聯(lián),QSPI?,串行,SPI?
電壓電源: 模擬和數(shù)字
電源電壓: 2.3 V ~ 5.25 V,4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
Data Sheet
AD7606/AD7606-6/AD7606-4
Rev. C | Page 25 of 36
TYPICAL CONNECTION DIAGRAM
Figure 43 shows the typical connection diagram for the AD7606/
AD7606-6/AD7606-4. There are four AVCC supply pins on the
part, and each of the four pins should be decoupled using a 100 nF
capacitor at each supply pin and a 10 F capacitor at the supply
source. The AD7606/AD7606-6/AD7606-4 can operate with the
internal reference or an externally applied reference. In this
configuration, the AD7606 is configured to operate with the
internal reference. When using a single AD7606/AD7606-6/
AD7606-4 device on the board, the REFIN/REFOUT pin
should be decoupled with a 10 F capacitor. Refer to the
Internal/External Reference section when using an application
with multiple AD7606/AD7606-6/AD7606-4 devices. The
REFCAPA and REFCAPB pins are shorted together and
decoupled with a 10 F ceramic capacitor.
The VDRIVE supply is connected to the same supply as the
processor. The VDRIVE voltage controls the voltage value of the
output logic signals. For layout, decoupling, and grounding
hints, see the Layout Guidelines section.
After supplies are applied to the AD7606/AD7606-6/AD7606-4,
a reset should be applied to the AD7606/AD7606-6/AD7606-4
to ensure that it is configured for the correct mode of operation.
POWER-DOWN MODES
Two power-down modes are available on the AD7606/AD7606-6/
AD7606-4: standby mode and shutdown mode. The STBY pin
controls whether the AD7606/AD7606-6/AD7606-4 are in
normal mode or in one of the two power-down modes.
The power-down mode is selected through the state of the
RANGE pin when the STBY pin is low. Table 7 shows the
configurations required to choose the desired power-down mode.
When the AD7606/AD7606-6/AD7606-4 are placed in standby
mode, the current consumption is 8 mA maximum and power-
up time is approximately 100 s because the capacitor on the
REFCAPA and REFCAPB pins must charge up. In standby mode,
the on-chip reference and regulators remain powered up, and
the amplifiers and ADC core are powered down.
When the AD7606/AD7606-6/AD7606-4 are placed in shutdown
mode, the current consumption is 6 A maximum and power-up
time is approximately 13 ms (external reference mode). In shut-
down mode, all circuitry is powered down. When the AD7606/
AD7606-6/AD7606-4 are powered up from shutdown mode,
a RESET signal must be applied to the AD7606/AD7606-6/
AD7606-4 after the required power-up time has elapsed.
Table 7. Power-Down Mode Selection
Power-Down Mode
STBY
RANGE
Standby
0
1
Shutdown
0
AVCC
AGND
VDRIVE
+
REFIN/REFOUT
DB0 TO DB15
CONVST A, CONVST B
CS
RD
BUSY
RESET
AD7606
1F
10F
100nF
DIGITAL SUPPLY
VOLTAGE +2.3V TO +5.25V
ANALOG SUPPLY
VOLTAGE 5V1
EIGHT ANALOG
INPUTS V1 TO V8
PARALLEL
INTERFACE
1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48).
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AVCC PIN 37 AND PIN 38.
2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
REGCAP2
+
10F
REFCAPA
REFCAPB
OS 2
OS 1
OS 0
OVERSAMPLING
100nF
V1
PAR/SER SEL
STBY
REF SELECT
RANGE
V2
V3
V4
V5
V6
V7
V8
REFGND
V1GND
V2GND
V3GND
V4GND
V5GND
V6GND
V7GND
V8GND
VDRIVE
08479-
041
M
ICRO
P
RO
CE
S
O
R/
M
ICRO
CO
NV
E
RT
E
R/
DS
P
Figure 43. AD7606 Typical Connection Diagram
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