(VDD = +5 V, VREF
參數(shù)資料
型號(hào): AD7575JPZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 0K
描述: IC ADC 8BIT LC2MOS W/HOLD 20PLCC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 8
采樣率(每秒): 50k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 15mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 20-PLCC(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
REV. B
–2–
AD7575–SPECIFICATIONS
(VDD = +5 V, VREF = +1.23 V, AGND = DGND = 0 V; fCLK = 4 MHz external;
all specifications TMIN to TMAX unless otherwise noted)
Parameter
J, A Versions
1
K, B Versions
S Version
T Version
Units
Conditions/Comments
ACCURACY
Resolution
8
Bits
Total Unadjusted Error
±2
±1
±2
±1
LSB max
Relative Accuracy
±1
±1/2
±1
±1/2
LSB max
Minimum Resolution for Which
No Missing Codes Is Guaranteed
8
Bits max
Full-Scale Error
+25
°C
±1
LSB max
Full-Scale TC Is Typically 5 ppm/
°C
TMIN to TMAX
±1
LSB max
Offset Error
2
+25
°C
±1/2
LSB max
Offset TC Is Typically 5 ppm/
°C
TMIN to TMAX
±1/2
LSB max
ANALOG INPUT
Voltage Range
0 to 2 VREF
0 to 2 VREF 0 to 2 VREF
Volts
1 LSB = 2 VREF/256; See Figure 16
DC Input Impedance
10
M
min
Slew Rate, Tracking
0.386
V/
s max
SNR
3
45
dB min
VIN = 2.46 V p-p @ 10 kHz; See Figure 11
REFERENCE INPUT
VREF (For Specified Performance)
1.23
Volts
±5%
IREF
500
A max
LOGIC INPUTS
CS, RD
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
2.4
V min
IIN, Input Current
+25
°C
±1
A max
VIN = 0 or VDD
TMIN to TMAX
±10
A max
VIN = 0 or VDD
CIN, Input Capacitance
3
10
pF max
CLK
VlNL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
2.4
V min
IINL, Input Low Current
700
800
A max
VINL = 0 V
IINH, Input High Current
700
800
A max
VINH = VDD
LOGIC OUTPUTS
BUSY, DB0 to DB7
VOL, Output Low Voltage
0.4
V max
ISINK = 1.6 mA
VOH, Output High Voltage
4.0
V min
ISOURCE = 40 A
DB0 to DB7
Floating State Leakage Current
±1
±10
A max
VOUT = 0 to VDD
Floating State Output Capacitance
3
10
pF max
CONVERSION TIME
4
With External Clock
5
sf
CLK = 4 MHz
With Internal Clock, TA = +25°C5
5
s min
Using Recommended Clock
15
s max
Components Shown in Figure 15
POWER REQUIREMENTS
5
VDD
+5
Volts
±5% for Specified Performance
IDD
6
7
mA max
Typically 3 mA with VDD = +5 V
Power Dissipation
15
mW typ
Power Supply Rejection
±1/4
LSB max
4.75 V
≤ V
DD ≤ 5.25 V
NOTES
1Temperature ranges are as follows:
J, K Versions; 0
°C to +70°C
A, B Versions; –25
°C to +85°C
S, T Versions; –55
°C to +125°C
2Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB.
3Sample tested at +25
°C to ensure compliance.
4Accuracy may degrade at conversion times other than those specified.
5Power supply current is measured when AD7575 is inactive i.e., when CS = RD = BUSY = logic HIGH.
Specifications subject to change without notice.
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