參數(shù)資料
型號: AD7564
廠商: Analog Devices, Inc.
英文描述: +3.3 V/+5 V, Low Power, Quad 12-Bit DAC(LC2MOS低功耗四通道12位D/A轉(zhuǎn)換器)
中文描述: 3.3伏/ 5伏,低功耗,四路12位DAC(LC2MOS低功耗四通道12位的D / A轉(zhuǎn)換器)
文件頁數(shù): 7/16頁
文件大?。?/td> 404K
代理商: AD7564
–7–
REV. A
3
AD7564
PIN DESCRIPTIONS
Pin
Number
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
DGND
I
OUT2
C
V
DD
I
OUT1
C
R
FB
C
V
REF
C
I
OUT2
D
I
OUT1
D
R
FB
D
V
REF
D
SDOUT
CLR
LDAC
Digital Ground.
I
OUT2
terminal for DAC C. This should normally connect to the signal ground of the system.
Positive power supply. This is +5 V
±
5%.
I
OUT1
terminal for DAC C.
Feedback resistor for DAC C.
DAC C reference input.
I
OUT2
terminal for DAC D. This should normally connect to the signal ground of the system.
I
OUT1
terminal for DAC D.
Feedback resistor for DAC D.
DAC D reference input.
This shift register output allows multiple devices to be connected in a daisy chain configuration.
Asynchronous
CLR
input. When this input is taken low, all DAC latches are loaded with all 0s.
Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously
updated with the contents of the input latches.
Level-triggered control input (active low). This is the frame synchronization signal for the input data.
When
FSIN
goes low, it enables the input shift register, and data is transferred on the falling edges of
CLKIN. If the address bits are valid, the 12-bit DAC data is transferred to the appropriate input
latch on the sixteenth falling edge after
FSIN
goes low.
Serial data input. The device accepts a 16-bit word. DB0 and DB1 are DAC select bits. DB2 and
DB3 are device address bits. DB4 to DB15 contain the 12-bit data to be loaded to the selected
DAC.
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.
Device address pin. This input in association with A0 gives the device an address. If DB2 and DB3
of the serial input stream do not correspond to this address, the data which follows is ignored and
not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
Device address pin. This input in association with A1 gives the device an address.
DAC A reference input.
Feedback resistor for DAC A.
I
OUT1
terminal for DAC A.
I
OUT2
terminal for DAC A. This should normally connect to the signal ground of the system.
DAC B reference input.
Feedback resistor for DAC B.
I
OUT1
terminal for DAC B.
No Connect pin.
This pin connects to the back gates of the current steering switches. It should be connected to the
signal ground of the system.
I
OUT2
terminal for DAC B. This should normally connect to the signal ground of the system.
14
FSIN
15
SDIN
16
17
CLKIN
A1
18
19
20
21
22
23
24
25
26
27
A0
V
REF
A
R
FB
A
I
OUT1
A
I
OUT2
A
V
REF
B
R
FB
B
I
OUT1
B
N/C
AGND
28
I
OUT2
B
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