參數(shù)資料
型號(hào): AD7545
廠商: Analog Devices, Inc.
英文描述: CMOS 12-Bit Buffered Multiplying DAC(12位緩沖乘法D/A轉(zhuǎn)換器)
中文描述: 的CMOS 12位緩沖乘法DAC(12位緩沖乘法的D / A轉(zhuǎn)換器)
文件頁(yè)數(shù): 2/3頁(yè)
文件大?。?/td> 143K
代理商: AD7545
–2–
REV. A
AD7545–SPECIFICATIONS
200
200
TECHNCAL
DATA
13.5
V
DD
= +5 V
Limits
V
DD
= +15 V
Limits
T
A
= + 25
8
C
Parameter
Version
T
A
= + 25
8
C T
MIN,
T
MAX1
T
MIN,
T
MAX1
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
All
J, A, S
K, B, T
L, C, U
GL, GC, GU
J, A, S
K, B, T
L, C, U
GL, GC, GU
J, A, S
K, B, T
L, C, U
GL, GC, GU
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
20
±
10
±
5
±
1
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
20
±
10
±
6
±
2
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
25
±
15
±
10
±
6
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
25
±
15
±
10
±
7
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Differential Nonlinearity
10-Bit Monotonic T
MIN
to T
MAX
12-Bit Monotonic T
MIN
to T
MAX
12-Bit Monotonic T
MIN
to T
MAX
12-Bit Monotonic T
MIN
to T
MAX
DAC Register Loaded with
1111 1111 1111
Gain Error Is Adjustable Using
the Circuits of Figures 4, 5, and 6
Gain Error (Using Internal RFB)
2
Gain Temperature Coefficient
3
Gain/
Temperature
DC Supply Rejection
3
Gain/
V
DD
Output Leakage Current at OUT1
All
±
5
±
5
±
10
±
10
ppm/
°
C max
Typical Value is 2 ppm/
°
C for V
DD
= +5 V
All
J, K, L, GL
A, B, C, GC
S, T, U, GU
0.015
10
10
10
0.03
50
50
200
0.01
10
10
10
0.02
50
50
200
% per % max
nA max
nA max
nA max
V
DD
=
±
5%
DB0–DB11 = 0 V;
WR
,
CS
= 0 V
DYNAMIC PERFORMANCE
Current Settling Time
3
All
2
2
2
2
μ
s max
To 1/2 LSB. OUT1 Load = 100
. DAC
Output Measured from Falling Edge of
WR
,
CS
= 0.
Propagation Delay
3
(from Digital
Input Change to 90%
of Final Analog Output)
Digital-to-Analog Glitch Inpulse
AC Feedthrough
5
At OUT1
All
All
300
400
250
250
ns max
nV sec typ
OUT1 Load = 100
, C
EXT
= 13 pF
4
V
REF
= AGND
All
5
5
5
5
mV p-p typ
V
REF
=
±
10 V, 10 kHz Sinewave
REFERENCE INPUT
Input Resistance
(Pin 19 to GND)
All
7
25
7
25
7
25
7
25
k
min
k
max
Input Resistance TC = –300 ppm/
°
C typ
Typical Input Resistance = 11 k
ANALOG OUTPUT
Output Capacitance
3
C
OUT1
C
OUT1
DIGITAL INPUTS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Current
6
I
IN
Input Capacitance
3
DB0–DB11
WR
,
CS
SWITCHING CHARACTERISTICS
7
Chip Select to Write Setup Time
t
CS
Chip Select to Write Hold Time
t
CH
Write Pulse Width
t
WR
All
70
200
70
200
pF max
pF max
DB0–DB11 = 0 V,
WR
,
CS
= 0 V
DB0–DB11 = V
DD
,
WR
,
CS
= 0 V
All
2.4
2.4
13.5
V min
All
0.8
0.8
1.5
1.5
V max
All
±
1
±
10
±
1
±
10
μ
A max
V
IN
= 0 or V
DD
All
All
5
20
5
20
5
20
5
20
pF max
pF max
V
IN
= 0
V
IN
= 0
All
280
200
380
270
180
120
200
150
ns min
ns typ
See Timing Diagram
All
0
0
0
0
ns min
All
250
175
140
100
400
280
210
150
160
100
90
60
240
170
120
80
ns min
ns typ
ns min
ns typ
t
CS
t
WR
, t
CH
0
Data Setup Time
t
DS
Data Hold Time
t
DH
POWER SUPPLY
I
DD
All
All
10
10
10
10
ns min
All
2
100
10
2
500
10
2
100
10
2
500
10
mA max
μ
A max
μ
A typ
All Digital Inputs V
IL
or V
IH
All Digital Inputs 0 V to V
DD
All Digital Inputs 0 V to V
DD
NOTES
1
Temperature range as follows: J, K, L, GL versions, 0
°
C to +70
°
C; A, B, C, GC versions, –25
°
C to +85
°
C; S, T, U GU versions, –55
°
C to +125
°
C.
2
This includes the effect of 5 ppm max gain TC.
3
Guaranteed but not tested.
4
DB0–DB11 = 0 V to V
DD
or V
DD
to 0 V.
5
Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.
6
Logic inputs are MOS gates. Typical input current (+25
°
C) is less than 1 nA.
7
Sample tested at +25
°
C to ensure compliance.
Specifications subject to change without notice.
(V
REF
= +10 V, V
OUT1
= O V, AGND = DGND unless otherwise noted)
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