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參數(shù)資料
| 型號： | AD7531LD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 12-Bit Binary Multiplying D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.5 us SETTLING TIME, 12-BIT DAC, CDIP18 |
| 封裝： | CERAMIC, DIP-18 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 264K |
| 代理商： | AD7531LD |
Typical Applications
The following applications are also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.
Operational Amplifier Bias Current
(Figure 3)
The op amp bias current, I
b
, flows through the 15k internal
feedback resistor. BI-FET op amps have low I
b
and, there-
fore, the 15k
c
I
b
error they introduce is negligible; they are
strongly recommended for the DAC1020 applications.
V
OS
Considerations
The output impedance, R
OUT
, of the DAC is modulated by
the digital input code which causes a modulation of the op-
erational amplifier output offset. It is therefore recommend-
ed to adjust the op amp V
OS
. R
OUT
is
E
15k if more than 4
digital inputs are high; R
OUT
is
E
45k if a single digital input
is high, and R
OUT
approaches infinity if all inputs are low.
Operational Amplifier V
OS
Adjust
(Figure 3)
Connect all digital inputs, A1–A10, to ground and adjust the
potentiometer to bring the op amp V
OUT
pin to within
g
1
mV from ground potential. If V
REF
is less than 10V, a finer
V
OS
adjustment is required. It is helpful to increase the reso-
lution of the V
OS
adjust procedure by connecting a 1 k
X
resistor between the inverting input of the op amp to
ground. After V
OS
has been adjusted, remove the 1 k
X
.
Full-Scale Adjust
(Figure 4)
Switch high all the digital inputs, A1–A10, and measure the
op amp output voltage. Use a 500
X
potentiometer, as
shown, to bring
ll
V
OUT
ll
to a voltage equal to V
REF
c
1023/1024.
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER
Op Amp Family
C
F
R
i
P
V
W
Circuit Settling
Time, t
s
Circuit Small
Signal BW
LF357
LF356
LF351
LM741
10 pF
22 pF
24 pF
0
2.4k
%
%
%
25k
25k
10k
10k
V
a
V
a
V
b
V
b
1.5
m
s
3
m
s
4
m
s
40
m
s
1M
0.5M
0.5M
200 kHz
TL/H/5689–3
V
OUT
e b
V
REF
#
A1
2
a
A2
4
a
A3
8
a
# # #
A10
1024
J
b
10V
s
V
REF
s
10V
0
s
V
OUT
s
b
1023
REF
where A
N
e
1 if the A
N
digital input is high
A
N
e
0 if the A
N
digital input is low
FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying
Configuration (Digital Attenuator)
http://www.national.com
4
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