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參數(shù)資料
| 型號： | AD7524LNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT MULTIPLYING 16DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 設(shè)置時間： | 250ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 4M |
AD7524
REV. B
–4–
WRITE MODE
When CS and WR are both LOW, the AD7524 is in the
WRITE mode, and the AD7524 analog output responds to data
activity at the DB0–DB7 data bus inputs. In this mode, the
AD7524 acts like a nonlatched input D/A converter.
HOLD MODE
When either CS or WR is HIGH, the AD7524 is in the HOLD
mode. The AD7524 analog output holds the value correspond-
ing to the last digital input present at DB0–DB7 prior to WR or
CS
assuming the HIGH state.
MODE SELECTION TABLE
CS
WR
Mode
DAC Response
L
Write
DAC responds to data bus
(DB0–DB7) inputs.
H
X
Hold
Data bus (DB0–DB7) is
Locked Out:
X
H
Hold
DAC holds last data present
when WR or CS assumed
HIGH state.
L = Low State, H = High State, X = Don't Care.
WRITE CYCLE TIMING DIAGRAM
Figure 3. Supply Current vs. Logic Level
Typical plots of supply current, IDD, versus logic input voltage,
VIN, for VDD = +5 V and VDD = +15 V are shown above.
CIRCUIT DESCRIPTION
CIRCUIT INFORMATION
The AD7524, an 8-bit multiplying D/A converter, consists of a
highly stable thin film R-2R ladder and eight N-channel current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
Figure 1. Functional Diagram
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuit for all digital inputs LOW is shown in
Figures 2. In Figure 2 with all digital inputs LOW, the refer-
ence current is switched to OUT2. The current source ILEAKAGE
is composed of surface and junction leakages to the substrate
while the
1
256
current source represents a constant 1-bit cur-
rent drain through the termination resistor on the R-2R ladder.
The “ON” capacitance of the output N-channel switches is
120 pF, as shown on the OUT2 terminal. The “OFF” switch
capacitance is 30 pF, as shown on the OUT1 terminal. Analysis
of the circuit for all digital inputs high is similar to Figure 2
however, the “ON” switches are now on terminal OUT1, hence
the 120 pF appears at that terminal.
Figure 2. AD7524 DAC Equivalent Circuit—All Digital
Inputs Low
INTERFACE LOGIC INFORMATION
MODE SELECTION
AD7524 mode selection is controlled by the CS and WR inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7524LP | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 8-bit 20-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:CMOS CONVERTER IC - Bulk |
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| AD7524LPZ | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 8-bit 20-Pin PLCC |
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