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參數資料
| 型號： | AD7492BRU |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators |
| 中文描述： | 雙通道高效率，低噪聲，同步降壓型開關穩(wěn)壓器 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 194K |
| 代理商： | AD7492BRU |
REV. 0
AD7492
–10–
100nF
PARALLELED
INTERFACE
2.5V
0V TO 2.5V
1nF
10 F
0.1 F
47 F
AD7492
AV
DD
V
DRIVE
DV
DD
REF OUT
DB0
–
DB9 (DB11)
CS
CONVST
RD
BUSY
V
IN
C/ P
ANALOG
SUPPLY
2.7V
–
5.25V
+
+
PS/
FS
Figure 5. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The designed
code transitions occur at successive integer LSB values (i.e.,
1 LSB, 2 LSB, etc.). The LSB size is = 2.5/4096 for the AD7492.
The ideal transfer characteristic for the AD7492 is shown in
Figure 6.
111...111
111...110
111...000
011...111
000...010
000...001
000...000
A
0V 1/2LSB
+V
REF
–
1LSB
ANALOG INPUT
1LSB = V
REF
/4096
Figure 6. Transfer Characteristic for 12 Bits
AC ACQUISITION TIME
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the V
IN
pin of the
ADC will cause the THD to degrade at high input frequencies.
Table I. Dynamic Performance Specifications
Typical Amplifier
Current
Consumption
Input
Buffers
SNR
500 kHz
THD
500 kHz
AD9631
AD797
69.5
69.6
80
81.6
17 mA
8.2 mA
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends it on the falling edge of the
CONVST
signal. At
the end of conversion there is a settling time associated with the
sampling circuit. This settling time lasts 120 ns. The analog
signal on V
IN
is also being acquired during this settling time;
therefore, the minimum acquisition time needed is 120 ns.
Figure 7 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3 represents
the source impedance of a buffer amplifier or resistive network,
R1 is an internal switch resistance, R2 is for bandwidth control,
and C1 is the sampling capacitor. C2 is back-plate capacitance
and switch parasitic capacitance.
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
R3
R1
125
V
IN
C1
22pF
C2
8pF
R2
636
Figure 7. Equivalent Analog Input Circuit
ANALOG INPUT
Figure 8 shows the equivalent circuit of the analog input struc-
ture of the AD7492. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. The capacitor C3 is typically
about 4 pF and can be primarily attributed to pin capacitance.
The resistor R1 is an internal switch resistance. This resistor is
typically about 125
. The capacitor C1 is the sampling capaci-
tor while R2 is used for bandwidth control.
R1
125
V
IN
C1
22pF
C2
8pF
R2
636
D1
D2
C3
4pF
V
DD
Figure 8. Equivalent Analog Input Circuit
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
data buffers are activated when both
CS
and
RD
are logic low.
At this point the contents of the data register are placed onto the
data bus. Figure 9 shows the timing diagram for the parallel port.
Figure 10 shows the timing diagram for the parallel port when
CS
and
RD
are tied permanently low. In this setup, once the
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
It is important to point out that the data bus cannot change
state while the A/D is doing a conversion as this would have a
detrimental effect on the conversion in progress. The data out
lines will go three-state again when either the
RD
or
CS
line
goes high. Thus the
CS
can be tied low permanently, leaving the
RD
line to control conversion result access. Please reference the
V
DRIVE
section for output voltage levels.
OPERATING MODES
The AD7492 has two possible modes of operation depending on
the state of the
CONVST
pulse at the end of a conversion, Mode 1
and Mode 2.
Mode 1 (High-Speed Sampling)
In this mode of operation the
CONVST
pulse is brought high
before the end of conversion, i.e., before the BUSY goes low (see
Figure 10). If the
CONVST
pin is brought from high to low while
BUSY is high, the conversion is restarted. When operating in
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7492BRU-5 | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC, INTERNAL REF + CLOCK - Bulk |
| AD7492BRU-5-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
| AD7492BRU-5-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
| AD7492BRU-REEL | 功能描述:IC ADC 12BIT W/REF W/CLK 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯(lián) 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7492BRU-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC, INTERNAL REF + CLOCK - Tape and Reel |
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