參數(shù)資料
型號(hào)： AD7492AR
英文描述： 500kHz High Efficiency 6A Switching Regulator; Package: DD PAK; No of Pins: 7; Temperature Range: 0°C to +70°C
中文描述： 的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 194K
代理商： AD7492AR
REV. 0
AD7492
–14–
SHARC is a registered trademark of Analog Devices, Inc.
POWER SUPPLIES
Separate power supplies for AV
DD
and DV
DD
are desirable, but
if necessary, DV
DD
may share its power connection to AV
DD
.
The digital supply (DV
DD
) must not exceed the analog supply
(AV
DD
) by more than 0.3 V in normal operation.
MICROPROCESSOR INTERFACING
AD7492 to ADSP-2185 Interface
Figure 19 shows a typical interface between the AD7492 and the
ADSP-2185. The ADSP-2185 processor can be used in one of two
memory modes, Full Memory Mode and Host Mode. The Mode
C pin determines in which mode the processor works. The inter-
face in Figure 19 is set up to have the processor working in Full
Memory Mode, which allows full external addressing capabilities.
When the AD7492 has finished converting, the BUSY line
requests an interrupt through the
IRQ2
pin. The
IRQ2
interrupt
has to be set up in the interrupt control register as edge-sensitive.
The DMS (Data Memory Select) pin latches in the address of the
A/D into the address decoder. The read operation is thus started.
ADDRESS
DECODER
AD7492
ADSP-2185
*
A0
–
A15
DMS
IRQ2
RD
MODE C
D0
–
D23
CONVST
CS
RD
BUSY
DB0
–
DB9
(DB11)
ADDRESS BUS
DATA BUS
100k
*
ADDITIONAL PINS OMITTED FOR CLARITY
OPTIONAL
Figure 19. Interfacing to the ADSP-2185
AD7492 to ADSP-21065L Interface
Figure 20 shows a typical interface between the AD7492 and the
ADSP-21065L SHARC
processor. This interface is an example
of one of three DMA handshake modes. The
MS
X
control line
is actually three memory select lines. Internal ADDR
25
–
24
are
decoded into
MS
3-0
, these lines are then asserted as chip selects.
The
DMAR
1
(DMA Request 1) is used in this setup as the
interrupt to signal end of conversion. The rest of the interface is
standard handshaking operation.
AD7492
ADSP-21065L
*
ADDR
0
–
ADDR
23
RD
D0
–
D31
CONVST
RD
DB0
–
DB9
(DB11)
BUSY
ADDRESS BUS
DATA BUS
*
ADDITIONAL PINS OMITTED FOR CLARITY
OPTIONAL
DMAR
1
ADDRESS
LATCH
ADDRESS
BUS
ADDRESS
DECODER
MS
X
CS
Figure 20. Interfacing to ADSP-21065L
AD7492 to TMS320C25 Interface
Figure 21 shows an interface between the AD7492 and the
TMS320C25. The
CONVST
signal can be applied from the
TMS320C25 or from an external source. The BUSY line inter-
rupts the digital signal processor when conversion is completed.
The TMS320C25 does not have a separate
RD
output to drive
the AD7492
RD
input directly. This has to be generated from
the processor
STRB
and R/
W
outputs with the addition of some
glue logic. The
RD
signal is OR-gated with the
MSC
signal to
provide the WAIT state required in the read cycle for correct
interface timing. The following instruction is used to read the
conversion from the AD7492:
IN D,ADC
where
D
is Data Memory address and the
ADC
is the AD7492
address. The read operation must not be attempted during
conversion.
ADDRESS
DECODER
AD7492
TMS320C25
*
A0
–
A15
IS
STRB
R/
W
READY
DMD0
–
DMD15
CONVST
CS
RD
BUSY
DB0
–
DB9
(DB11)
ADDRESS BUS
*
ADDITIONAL PINS OMITTED FOR CLARITY
OPTIONAL
MSC
DATA BUS
Figure 21. Interfacing to the TMS320C25
AD7492 to PIC17C4x Interface
Figure 22 shows a typical parallel interface between the AD7492
and PIC17C42/43/44. The microcontroller sees the A/D as
another memory device with its own specific memory address on
the memory map. The
CONVST
signal can either be controlled
by the microcontroller or an external source. The BUSY signal
provides an interrupt request to the microcontroller when a con-
version ends. The INT pin on the PIC17C42/43/44 must be
configured to be active on the negative edge. PORTC and PORTD
of the microcontroller are bidirectional and used to address the
AD7492 and also to read in the 12-bit data. The
OE
pin on the
PIC can be used to enable the output buffers on the AD7492 and
preform a read operation.
*
ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
DECODER
ADDRESS
LATCH
OPTIONAL
PIC17C4x
*
AD0
–
AD15
OE
INT
AD74792
CONVST
CS
RD
BUSY
DB0
–
DB9
(DB11)
ALE
Figure 22. Interfacing to the PIC17C4x
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7492AR-5 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC, INTERNAL REF + CLOCK - Bulk 制造商:Analog Devices 功能描述:12BIT ADC 1MSPS SMD 7492 SOIC24
AD7492AR-5-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel
AD7492AR-5-REEL7 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel
AD7492AR-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC,INTERNAL REF + CLOCK - Tape and Reel
AD7492AR-REEL7 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC, INTERNAL REF + CLOCK - Tape and Reel
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