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參數(shù)資料
| 型號(hào)： | AD7492AR-5 |
| 英文描述： | A/D CONVERTER |
| 中文描述： | 的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 194K |
| 代理商： | AD7492AR-5 |
REV. 0
AD7492
TIMING SPECIFICATIONS
1
–4–
Limit at T
MIN
, T
MAX
AD7492
Parameter
AD7492-5
2
Unit
Description
t
CONVERT
t
WAKEUP
880
20
3
500
10
10
40
0
0
20
15
8
0
120
100
680
20
3
500
10
10
N/A
0
0
20
15
8
0
120
100
ns max
μ
s max
μ
s max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
Partial Sleep Wake-Up Time
Full Sleep Wake-Up Time
CONVST
Pulsewidth
CONVST
to BUSY Delay, V
DD
= 5 V
CONVST
to BUSY Delay, V
DD
= 3 V
BUSY to
CS
Setup Time
CS
to
RD
Setup Time
RD
Pulsewidth
Data Access Time after Falling Edge of
RD
Bus Relinquish Time after Rising Edge of
RD
CS
to
RD
Hold Time
Acquisition Time
Quiet Time
t
1
t
2
t
3
t
44
t
5
t
64
t
75
t
8
t
9
t
10
NOTES
1
Sample tested at 25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
Figure 1.
2
The AD7492-5 is specified with V
= 4.75 V to 5.25 V.
3
This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20
μ
s, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
I
OL
200 A
I
OH
C
L
50pF
TO OUTPUT
PIN
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
(V
DD
= 2.7 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
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| AD7492AR-5-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel |
| AD7492AR-5-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel |
| AD7492AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC,INTERNAL REF + CLOCK - Tape and Reel |
| AD7492AR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT PARALLEL 24SOIC W - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC, INTERNAL REF + CLOCK - Tape and Reel |
| AD7492ARU | 功能描述:IC ADC 12BIT W/REF W/CLK 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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