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參數(shù)資料
| 型號： | AD7490BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 16CHAN 28TSSOP |
| 產(chǎn)品變化通告： | IDD Specification Change 17/Jun/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個單端，單極 |
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AD7490
Data Sheet
Rev. D | Page 12 of 28
INTERNAL REGISTER STRUCTURE
CONTROL REGISTER
The control register on the AD7490 is a 12-bit, write-only
register. Data is loaded from the DIN pin of the AD7490 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time as the conversion result is read from the part.
The data transferred on the DIN line corresponds to the
AD7490 configuration for the next conversion. This requires
16 serial clocks for every data transfer. Only the information
provided on the first 12 falling clock edges (after the CS falling
edge) is loaded to the control register. MSB denotes the first bit
in the data stream. The bit functions are outlined in Table 5.
Table 5. Control Register
MSB
LSB
11
10
9
8
7
6
5
4
3
2
1
0
WRITE
SEQ
ADD3
ADD2
ADD1
ADD0
PM1
PM0
SHADOW
WEAK/TRI
RANGE
CODING
Table 6. Control Register Bit Functions
Bit
Name
Description
11
WRITE
The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register or not. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the
remaining 11 bits are not loaded to the control register, and it remains unchanged.
10
SEQ
The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer
function and access the Shadow register (see Table 9).
9 to 6
ADD3 to
ADD0
These four address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted on in the next serial transfer, or they may select the final channel in a consecutive
sequence, as described in Table 9. The selected input channel is decoded as shown in Table 7. The next channel to
be converted on is selected by the mux on the 14th SCLK falling edge. The address bits corresponding to the
conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section).
5, 4
PM1, PM0
Power management bits. These two bits decode the mode of operation of the AD7490, as shown in Table 8.
3
SHADOW
The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer
function and access the Shadow register (see Table 9).
2
WEAK/TRI
This bit selects the state of the DOUT line at the end of the current serial transfer. If it is set to 1, the DOUT line is
weakly driven to the ADD3 channel address bit of the ensuing conversion. If this bit is set to 0, DOUT returns to
three-state at the end of the serial transfer. See the Control Register section for more details.
1
RANGE
This bit selects the analog input range to be used on the AD7490. If it is set to 0, the analog input range extends
from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion).
For 0 V to 2 × REFIN, VDD = 4.75 V to 5.25 V.
0
CODING
This bit selects the type of output coding used by the AD7490 for the conversion result. If this bit is set to 0, the
output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight
binary (for the next conversion).
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