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| 型號(hào)： | AD7490BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 16CHAN 32LFCSP |
| 產(chǎn)品變化通告： | IDD Specification Change 17/Jun/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個(gè)單端，單極 |
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AD7490
Data Sheet
Rev. D | Page 18 of 28
TYPICAL CONNECTION DIAGRAM
Figure 21 shows a typical connection diagram for the AD7490.
In this setup, the AGND pin is connected to the analog ground
decoupled 2.5 V supply from a reference source, the AD780, to
provide an analog input range of 0 V to 2.5 V (if the RANGE bit
is 1) or 0 V to 5 V (if the RANGE bit is 0). Although the AD7490
is connected to a VDD of 5 V, the serial interface is connected to
a 3 V microprocessor. The VDRIVE pin of the AD7490 is connected
to the same 3 V supply of the microprocessor to allow a 3 V
logic interface (see the Digital Input section). The conversion
result is output in a 16-bit word. This 16-bit data stream
consists of four address bits, indicating which channel the
conversion result corresponds to, followed by the 12 bits of
conversion data. For applications where power consumption is
of concern, the power-down modes should be used between
conversions or bursts of several conversions to improve power
performance (see the Modes of Operation section).
02691-
020
0.1F
10F
5V
SUPPLY
SERIAL
INTERFACE
3V
SUPPLY
C
ON
TR
OLLE
R
/
PR
O
C
ESSO
R
AD7490
0.1F
0V TO REFIN
AGND
SCLK
DOUT
CS
DIN
VIN0
VDD
VDRIVE
REFIN
VIN15
10F
2.5V
AD780
Figure 21. Typical Connection Diagram
Analog Input Channels
Any one of 16 analog input channels can be selected for conver-
sion by programming the multiplexer with the ADD3 to ADD0
address bits in the control register. The channel configurations
are shown in Table 7. The AD7490 can also be configured to
automatically cycle through a number of channels, as selected.
The sequencer feature is accessed via the SEQ and SHADOW
bits in the control register (see Table 9). The AD7490 can be
programmed to continuously convert on a selection of channels
in ascending order. The sequence of analog input channels to be
converted on is selected through programming the relevant bits
in the Shadow register (see Table 10). The next serial transfer
then acts on the sequence programmed by executing a conver-
sion on the lowest channel in the selection.
The next serial transfer results in a conversion on the next
highest channel in the sequence, and so on. It is not necessary
to write to the control register once a sequencer operation has
been initiated. The WRITE bit must be set to 0 or the DIN line
tied low to ensure the control register is not accidentally over-
written or the sequence operation interrupted. If the control
register is written to at any time during the sequence, it must be
ensured that the SEQ and SHADOW bits are set to 1, 0 to avoid
interrupting the automatic conversion sequence. This pattern
continues until such time as the AD7490 is written to and the
SEQ and SHADOW bits are configured with any bit combination
except 1, 0. On completion of the sequence, the AD7490 sequencer
returns to the first selected channel in the Shadow register and
commences the sequence again, if uninterrupted.
Rather than selecting a particular sequence of channels, a number
of consecutive channels beginning with Channel 0 can also be
programmed via the control register alone without needing to
write to the Shadow register. This is possible if the SEQ and
SHADOW bits are set to 1, 1. The ADD3 through ADD0 channel
address bits then determine the final channel in the consecutive
sequence. The next conversion is on Channel 0, then Channel 1,
and so on until the channel selected via the ADD3 through
ADD0 address bits is reached. The cycle begins again on the
next serial transfer, provided the WRITE bit is set to low; or, if
high, that the SEQ and SHADOW bits are set to 1, 0, then the
ADC continues its preprogrammed automatic sequence uninter-
rupted. Regardless of which channel selection method is used,
the 16-bit word output from the AD7490 during each conversion
always contains the channel address that the conversion result
corresponds to, followed by the 12-bit conversion result (see the
Serial Interface section).
Digital Input
The digital inputs applied to the AD7490 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted
by the VDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If CS, DIN, or SCLK is applied before VDD,
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to VDD.
VDRIVE
The AD7490 also has the VDRIVE feature. VDRIVE controls the
voltage at which the serial interface operates. VDRIVE allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7490 is operated with a VDD of 5 V, the VDRIVE
pin can be powered from a 3 V supply. The AD7490 has better
dynamic performance with a VDD of 5 V, while still being able
to interface to 3 V processors. Care should be taken to ensure
that VDRIVE does not exceed VDD by more than 0.3 V (see the
Absolute Maximum Ratings section).
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