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參數資料
| 型號： | AD7477AARMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 1MSPS 8-MSOP |
| 標準包裝： | 3,000 |
| 位數： | 10 |
| 采樣率（每秒）： | 1M |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個單端，單極 |
| 配用： | EVAL-AD7477CBZ-ND - BOARD EVALUATION FOR AD7477 |
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AD7476A/AD7477A/AD7478A
Rev. F | Page 22 of 28
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
serial clock has the first leading zero provided and also clocks
out the second leading zero. For the AD7476A, the final bit in
the data transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK clocks out the second leading zero, which can be read in
the first rising edge. However, the first leading zero that was
clocked out when CS went low will be missed, unless it was not
read in the first falling edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after one SCLK falling edge has elapsed, CS
clocks out the first leading zero as it did before, and it can be
read in the SCLK rising edge. The next SCLK falling edge clocks
out the second leading zero, and it can be read in the following
rising edge.
AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE
For the AD7478A, if CS is brought high in the 12th rising edge
after four leading zeros and eight bits of the conversion have
been provided, the part can achieve a 1.2 MSPS throughput
rate. For the AD7478A, the track-and-hold goes back into track
in the 11th rising edge. In this case, a fSCLK = 20 MHz and a
throughput of 1.2 MSPS give a cycle time of
t2 + 10.5(1/fSCLK)+ tACQ = 833 ns
With t2 = 10 ns min, this leaves tACQ to be 298 ns. This 298 ns
satisfies the requirement of 225 ns for tACQ.
0.5 (1/fSCLK) + t8 + tQUIET
where t8 = 36 ns maximum.
This allows a value of 237 ns for tQUIET, satisfying the minimum
requirement of 50 ns.
SCLK
t1
1
5
11
SDATA
THREE-STATE
DB7
DB6
DB0
ZERO
4 LEADING ZEROS
2
3
t2
t8
12
1/THROUGHPUT
tACQ
10.5(1/
fSCLK)
tCONVERT
tQUIET
B
THREE-STATE
CS
4
02930-027
Z
Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7477AARMZ-REEL7 | 功能描述:IC ADC 10BIT 1MSPS 8-MSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:2,500 系列:- 位數:16 采樣率（每秒）:15 數據接口:MICROWIRE?，串行，SPI? 轉換器數目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應商設備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7477ART | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7477ART-500RL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 6-Pin SOT-23 T/R |
| AD7477ART-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 6-Pin SOT-23 T/R 制造商:Rochester Electronics LLC 功能描述:10-BIT ADC IN SOT I.C. - Tape and Reel |
| AD7477ART-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 6-Pin SOT-23 T/R |
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