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REV. A
–12–
AD7476A/AD7477A/AD7478A
CIRCUIT INFORMATION
The AD7476A/AD7477A/AD7478A are fast, micropower,
12-/10-/8-bit, single-supply A/D converters, respectively. The
parts can be operated from a 2.35 V to 5.25 V supply. When
operated from either a 5 V supply or a 3 V supply, the AD7476A/
AD7477A/AD7478A are capable of throughput rates of 1 MSPS
when provided with a 20 MHz clock.
The AD7476A/AD7477A/AD7478A provide the user with an
on-chip track-and-hold, A/D converter and a serial interface
housed in a tiny 6-lead SC70 or 8-lead MSOP package, which
offers the user considerable space-saving advantages over
alternative solutions. The serial clock input accesses data from
the part but also provides the clock source for the successive
approximation A/D converter. The analog input range is 0 to V
DD
.
The ADC does not require an external reference or a reference
on-chip. The reference for the AD7476A/AD7477A/AD7478A is
derived from the power supply and thus gives the widest dynamic
input range.
The AD7476A/AD7477A/AD7478A also feature a power-down
option to allow power saving between conversions. The power-
down feature is implemented across the standard serial interface,
as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7476A/AD7477A/AD7478A is a successive approximation,
analog-to-digital converter based around a charge redistribution
DAC. Figures 4 and 5 show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on V
IN
.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW1
A
B
AGND
V
DD
/2
V
IN
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion, see Figure 5, SW2 will open and
SW1 will move to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 6 shows the ADC transfer function.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW1
A
B
AGND
V
DD
/2
V
IN
Figure 5. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476A/AD7477A/AD7478A is
straight binary.
The designed code transitions occur at the successive integer
LSB values, i.e., 1 LSB, 2 LSB, and so on. The LSB size is
V
DD
/4096 for the AD7476A, V
DD
/1024 for the AD7477A, and
V
DD
/256 for the AD7478A. The ideal transfer characteristic for
the AD7476A/AD7477A/AD7478A is shown in Figure 6.
000...000
0V
A
ANALOG INPUT
111...111
111...110
000...001
000...010
111...000
011...111
1LSB = V
DD
/256 (AD7478A)
1LSB
+V
DD
–1LSB
1LSB = V
DD
/1024 (AD7477A)
1LSB = V
DD
/4096 (AD7476A)
Figure 6. AD7476A/AD7477A/AD7478A
Transfer Characteristic