V
參數(shù)資料
型號(hào)： AD7476AYRMZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/29頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 2.35V 1MSPS 8-MSOP
設(shè)計(jì)資源： Output Channel Monitoring Using AD5380 (CN0008)
AD5382 Channel Monitor Function (CN0012)
AD5381 Channel Monitor Function (CN0013)
AD5383 Channel Monitor Function (CN0015)
AD5390/91/92 Channel Monitor Function (CN0030)
Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極
產(chǎn)品目錄頁面： 778 (CN2011-ZH PDF)
配用： EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A
AD7476A/AD7477A/AD7478A
Rev. F | Page 11 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
VDD
GND
VIN
CS
SDATA
SCLK
AD7476A/
AD7477A/
AD7478A
02930-005
Figure 5. 6-Lead SC70 Pin Configuration
8
7
6
5
1
2
3
4
NC = NO CONNECT
VDD
SDATA
VIN
GND
SCLK
NC
TOP VIEW
(Not to Scale)
AD7476A/
AD7477A/
AD7478A
CS
02930-006
Figure 6. 8-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Mnemonic
Description
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7476A/AD7477A/AD7478A and also frames the serial data transfer.
VDD
Power Supply Input. The VDD range for AD7476A/AD7477A/AD7478A is from 2.35 V to 5.25 V.
GND
Analog Ground. Ground reference point for all circuitry on AD7476A/AD7477A/AD7478A. Refer all analog input signals to this
GND voltage.
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
SDATA
Data Out. Logic output. The conversion result from AD7476A/AD7477A/AD7478A is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four
leading zeros followed by 12 bits of conversion data that are provided MSB first. The data stream from the AD7477A consists
of four leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided MSB first. The data stream
from the AD7478A consists of four leading zeros followed by 8 bits of conversion data followed by four trailing zeros that are
provided MSB first.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process of AD7476A/AD7477A/AD7478A.
NC
No Connect.
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