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參數(shù)資料
| 型號： | AD7475BR |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL LP 8-SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD7475/AD7495
Rev. B | Page 16 of 24
OPERATING MODES
The AD7475/AD7495 operating mode is selected by controlling
the logic state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. The point at which CS
is pulled high after the conversion has been initiated determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance,
because the user does not have to worry about any power-up
times with the AD7475/AD7495 remaining fully powered all
the time. Figure 19 shows the general diagram of the AD7475/
AD7495 operating in this mode.
The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure the part
remains fully powered-up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10
th SCLK falling
edge, but before the 16th SCLK falling edge, the part remains
powered up but the conversion is terminated and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result. CS
may idle high until the next conversion or may idle low until
sometime prior to the next conversion (effectively idling CS
low).
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed, by bringing CS low again.
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7475 is in partial
power-down, all analog circuitry is powered down except for
the bias current generator; and, in the case of the AD7495, all
analog circuitry is powered down except for the on-chip
reference and reference buffer.
To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the tenth falling edge of SCLK,
as shown in Figure 20. Once CS has been brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and SDATA goes back into three-state. If CS is
brought high before the second SCLK falling edge, the part
remains in normal mode and does not power down. This avoids
accidental power-down due to glitches on the CS line.
SCLK
FOUR LEADING ZEROS + CONVERSION RESULT
SDATA
1
16
10
CS
01684-B
-019
Figure 19. Normal Mode
SCLK
1
16
10
2
CS
01684-B
-020
Figure 20. Entering Partial Power-Down Mode
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