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參數(shù)資料
| 型號： | AD7470ARUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/21頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT PARLLEL 24TSSOP T/R |
| 標準包裝： | 1,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1.75M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
REV. B
AD7470/AD7472
–7–
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7470
NC = NO CONNECT
DB7
DB6
DB8
DB5
(MSB) DB9
DB4
AVDD
VDRIVE
REF IN
DVDD
VIN
DGND
AGND
DB3
CS
DB2
RD
DB1
CONVST
DB0 (LSB)
CLKIN
BUSY
NC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7472
DB9
DB8
DB10
DB7
(MSB) DB11
DB6
AVDD
VDRIVE
REF IN
DVDD
VIN
DGND
AGND
DB5
CS
DB4
RD
DB3
CONVST
DB2
CLKIN
DB1
BUSY
DB0 (LSB)
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
CS
Chip Select. Active low logic input used in conjunction with
RD to access the conversion result. The conversion
result is placed on the data bus following the falling edge of both
CS and RD. CS and RD are both connected to
the same AND gate on the input so the signals are interchangeable.
CS can be hardwired permanently low.
RD
Read Input. Logic input used in conjunction with
CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both
CS and RD. CS and RD are both connected to same
AND gate on the input so the signals are interchangeable.
CS and RD can be hardwired permanently low, in
which case the data bus is always active and the result of the new conversion is clocked out slightly before to the
BUSY line going low.
CONVST
Conversion Start Input. Logic input used to initiate conversion. The input track-and-hold amplifier goes from
track mode to hold mode on the falling edge of
CONVST, and the conversion process is initiated at this point.
The conversion input can be as narrow as 10 ns. If the
CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep
mode, the next rising edge of
CONVST wakes up the part. Wake-up time for the part is typically 1
s.
CLK IN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7472 takes 14 clock cycles, and conversion time for the AD7470 takes 12 clock cycles. The frequency of this
master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is
not converting, the clock-in pad is in three-state and thus no clock is going through the part.
BUSY
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after the
falling edge of
CONVST and stays high for the duration of conversion. Once conversion is complete and the con-
version result is in the output register, the BUSY line returns low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low. If the
CONVST
input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY.
REF IN
Reference Input. An external reference must be applied to this input. The voltage range for the external reference
is 2.5 V
±1% for specified performance.
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/
AD7472. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V
apart even on a transient basis. This supply should be decoupled to AGND.
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7470/
AD7472 aside from the output drivers. The DVDD and AVDD voltages should ideally be at the same potential and
must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7472 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD7470/AD7472: 1.75MSPS. 4mW 10-Bit/12-Bit SAR ADC Data Sheet (Rev. A. 3/00) |
| AD7472AR | 功能描述:IC ADC 12BIT PARALLEL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7472AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1.5Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 1.5MSPS PARALLEL ADC I.C. - Tape and Reel |
| AD7472AR-REEL7 | 功能描述:IC ADC 12BIT PARALLEL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7472ARU | 功能描述:IC ADC 12BIT PARALLEL 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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