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參數(shù)資料
| 型號： | AD7468BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | AD7468BRM |
–3–
REV. PrC
Parameter
B Version
1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 30 kHz Sine Wave,
Signal-to-Noise + Distortion (SINAD)
2
61
dB min
Total Harmonic Distortion (THD)
2
–73
dB max
Peak Harmonic or Spurious Noise (SFDR)
2
–74
dB max
Intermodulation Distortion (IMD)
2
fa = 29.1 kHz, fb = 29.9 kHz
Second Order Terms
–78
dB typ
Third Order Terms
–78
dB typ
Aperture Delay
10
ns typ
Aperture Jitter
30
ps typ
Full Power Bandwidth
TBD
MHz typ
@ 3 dB
Full Power Bandwidth
T B D
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
±1
LSB max
Differential Nonlinearity
±0.9
LSB max
Guaranteed No Missed Codes to 10 Bits
Offset Error
±1
LSB max
Gain Error
±1
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to VDD
V
DC Leakage Current
±1
A max
Input Capacitance
30
pF typ
LOGIC INPUTS
Input High Voltage, VINH
0.7(VDD)
V min
VDD = 1.8 to 3.6 V
Input Low Voltage, VINL
0.4
V max
Input Current, IIN, SCLK Pin
±1
A max
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
±1
A typ
Input Capacitance, CIN
2,3
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VDD – 0.2
V min
ISOURCE = 200 A;
Output Low Voltage, VOL
0.2
V max
ISINK = 200 A
Floating-State Leakage Current
±10
A max
Floating-State Output Capacitance
2,3
10
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
5
s max
12 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time
TBD
ns max
Throughput Rate
100
kSPS max
See Serial Interface Section
POWER REQUIREMENTS
V DD
1.8/3.6
V min/max
I DD
Digital I/Ps = 0 V or VDD
Normal Mode (Operational)
350
A max
VDD = 3 V . SCLK On or Off
200
A max
VDD = 1.8 V . SCLK On or Off
Power-Down Mode
0.5
A max
SCLK Off
80
A max
SCLK On
Power Dissipation
4
Normal Mode (Operational)
TBD
mW max
VDD = 3 V. fSAMPLE = 100 kSPS
TBD
mW max
VDD = 1.8 V. fSAMPLE = TBD
Power-Down
1.5
W max
VDD = 3 V. SCLK Off
0.9
W max
VDD = 1.8 V. SCLK Off
NOTES
1Temperaturerangesasfollows:BVersions:–40°Cto+85°C.
2SeeTerminology.
3Sampletestedat25°Ctoensurecompliance.
4SeePowerVersusThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
AD7467–SPECIFICATIONS1 (VDD = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; TA =
TMIN to TMAX, unless otherwise noted.)
pecifications
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