參數(shù)資料
型號(hào): AD7467BRM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187-AA, MSOP-8
文件頁數(shù): 15/15頁
文件大小: 171K
代理商: AD7467BRM
AD7466/AD7467/AD7468
–9–
REV. PrC
CIRCUIT INFORMATION
The AD7466/AD7467/AD7468 are fast, micro-power, 12/
10/8-bit, A/D converters respectively. The parts can be
operated from a +1.8 V to +3.6 V supply. When operated
from any supply voltage within this range, the AD7466/
AD7467/AD7468 is capable of throughput rates of 100
kSPS when provided with a 2 MHz clock.
The AD7466/AD7467/AD7468 provides the user with an
on-chip track/hold, A/D converter, and a serial interface
housed in a tiny 6-pin SOT-23 package, which offers the
user considerable space saving advantages over alternative
solutions. The serial clock input accesses data from the
part but also provides the clock source for the successive-
approximation A/D converter. The analog input range is 0
to VDD. An external reference is not required for the ADC
and neither is there a reference on-chip. The reference for
the AD7466/AD7467/AD7468 is derived from the power
supply and thus gives the widest dynamic input range.
The AD7466/AD7467/AD7468 also features an automatic
power-down mode option to allow power saving between
conversions. The power-down feature is implemented
across the standard serial interface as described in the
“Modes of Operation” section.
ADC TRANSFER FUNCTION
The output coding of the AD7466/AD7467/AD7468 is
straight binary. The designed code transitions occur at
successive integer LSB values (i.e., 1LSB, 2LSBs, etc.).
The LSB size is = VDD/4096 for the AD7466,the LSB size
is =
VDD/1024 for the AD7467, and the LSB size is =
VDD/256 for the AD7468 . The ideal transfer characteristic
for the AD7466/AD7467/AD7468 is shown in figure 10
below.
CONVERTER OPERATION
The AD7466/AD7467/AD7468 is a successive approxi-
mation analog-to-digital converter based around a charge
redistribution DAC. Figures 8 and 9 show simplified
schematics of the ADC. Figure 8 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in posi-
tion A, the comparator is held in a balanced condition and
the sampling capacitor acquires the signal on VIN.
When the ADC starts a conversion, see figure 9, SW2 will
open and SW1 will move to position B causing the com-
parator to become unbalanced. The Control Logic and
the Charge Redistribution DAC are used to add and sub-
tract fixed amounts of charge from the sampling capacitor
to bring the comparator back into a balanced condition.
When the comparator is rebalanced the conversion is com-
plete. The Control Logic generates the ADC output code.
Figure 10 shows the ADC transfer function.
Figure 8. ADC Acquisition Phase
Figure 9. ADC Conversion Phase
Figure 10. AD7466/67/68 Transfer Characteristic
CH AR GE
R E D I S T RI BU T I O N
DA C
V IN
V DD / 2
SA M P L I N G
CA P A C I T O R
C O M P ARA T O R
CO N T RO L
L O GIC
ACQ UI S I T I O N
PHAS E
SW 1
A
B
SW 2
AG N D
CHARGE
REDISTRIBUTION
DA C
VIN
VDD / 2
SAMPLING
CAPACITOR
COMPAR ATOR
CONTROL
LO GIC
CONVERSION
PHASE
SW1
A
B
SW2
AGND
000...000
0V
A
D
C
O
D
E
ANAL OG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
1LSB
+VDD-1LSB
1LSB = VDD/4096 (AD7466)
1LSB = VDD/1024 (AD7467)
1LSB = VDD/256 (AD7468)
pecifications
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