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參數(shù)資料
| 型號： | AD744 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision, 500 ns Settling BiFET Op Amp |
| 中文描述： | 精密，500納秒的建立BiFET運算放大器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 914K |
| 代理商： | AD744 |
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7440 - SPECIFICATIONS
–5–
AD7450A/AD7440
Parameter
Test Conditions/Comments
B Version
1
Units
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
2
888ns with an 18MHz SCLK
Sine Wave Input
Step Input
16
200
TBD
1
SCLK cycles
ns max
ns max
MSPS max
Throughput Rate
8
POWER REQUIREMENTS
V
DD
Range: 3 V+20%/-10%;
5 V ± 5% 2.7V/5.25V
Vmin/max
I
DD9,10
Normal Mode(Static)
Normal Mode (Operational)
SCLK On or Off
V
DD
= 4.75V to 5.25V,
1.38mW typ for 100ksps
9
V
DD
= 2.7 V to 3.6V,
0.53mW typ for 100ksps
9
SCLK On or Off
0.5
mA typ
1.8
mA max
1.25
1
mA max
μA max
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
V
DD
=5 V.
V
DD
=3 V.
V
DD
=5 V. SCLK On or Off
V
DD
=3 V. SCLK On or Off
9
3.75
5
3
mW max
mW max
μW max
μW max
Full Power-Down
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
Because the input spans of V
and V
are both V
, and they are 180° out of phase, the differential voltage is 2 x V
.
4
Common Mode Voltage. The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
specified in Figures tbd and tbd.
5
The AD7440 is functional with a reference input from100mV and for V
DD
= 5V, the reference can range up to 3.5V.
6
The AD7440 is functional with a reference input from100mV and for V
DD
= 3V, the reference range up to 2.2V.
7
Sample tested @ +25°C to ensure compliance.
8
See ‘Serial Interface Section’.
9
See POWER VERSUS THROUGHPUT RATE section.
10
Measured with a midscale DC input.
Specifications subject to change without notice.
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