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參數(shù)資料
| 型號： | AD7376ARUZ50-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL POT 50K 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 300 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 4.5 V ~ 33 V，±4.5 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD7376EBZ-ND - BOARD EVAL FOR AD7376 |
AD7376
Rev. D | Page 14 of 20
DAISY-CHAIN OPERATION
0
11
19-
027
CS
SDI
SERIAL
REGISTER
D
CK
Q
RS
SHDN
SDO
RS
CLK
Figure 27. Detailed SDO Output Schematic of the AD7376
Figure 27 shows the details of the serial data output pin (SDO).
SDO shifts out the SDI content in the previous frame; therefore,
it can be used for daisy-chaining multiple devices. The SDO pin
contains an open-drain N-Channel MOSFET and requires a
pull-up resistor if the SDO function is used.
Users need to tie the SDO pin of one package to the SDI pin of
the next package. For example, in Figure 28, if two AD7376s are
daisy-chained, a total of 14 bits of data are required for each
operation. The first set of seven bits goes to U2; the second set
of seven bits goes to U1. CS should be kept low until all 14 bits
are clocked into their respective serial registers. Then CS is
pulled high to complete the operation.
When daisy-chaining multiple devices, users may need to
increase the clock period because the pull-up resistor and the
capacitive loading at the SDO to SDI interface may induce a
time delay to subsequent devices.
AD7376
SDO
SDI
CLK
CS
AD7376
SDO
SDI
CLK
CS
C
5V
RPU
2.2kΩ
MOSI
SS
SCLK
0
11
19-
028
U1
U2
Figure 28. Daisy-Chain Configuration
ESD PROTECTION
All digital inputs are protected with a series input resistor and
an ESD structure shown in Figure 29. These structures apply to
digital input pins CS, CLK, SDI, RS, and SHDN.
INPUT
340Ω
LOGIC
PINS
VDD
GND
0
11
19-
029
Figure 29. Equivalent ESD Protection Circuit
All analog terminals are also protected by ESD protection
diodes, as shown in Figure 30.
VSS
VDD
A
W
B
0
11
19-
030
Figure 30. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD7376 VDD and VSS power supplies define the boundary
conditions for proper 3-terminal digital potentiometer oper-
ation. Applied signals present on Terminals A, B, and W that
are more positive than VDD or more negative than VSS will be
clamped by the internal forward-biased diodes (see Figure 30).
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (see Figure 30), it is
important to power VDD/VSS before applying voltage to
Terminals A, B, and W. Otherwise, the diodes are forward
biased such that VDD/VSS are powered unintentionally and affect
the system. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
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| AD7376EVAL | 制造商:Analog Devices 功能描述: |
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