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參數(shù)資料
| 型號： | AD7356YRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 12BIT 5MSPS 16TSSOP |
| 設(shè)計資源： | DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 59mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，雙極 |
AD7356
Rev. A | Page 10 of 20
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (1 LSB below
the first code transition) and full scale (1 LSB above the last
code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Negative Full-Scale Error
Negative full-scale error is the deviation of the first code
transition (00 … 000) to (00 … 001) from the ideal (that is,
VREF + 0.5 LSB) after the midscale error has been adjusted out.
Negative Full-Scale Error Match
Negative full-scale error match is the difference in negative full-
scale error between the two ADCs.
Midscale Error
Midscale error is the deviation of the midscale code transition
(011 … 111) to (100 … 000) from the ideal (that is, 0 V).
Midscale Error Match
Midscale error match is the difference in midscale error
between the two ADCs.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code
transition (111 … 110) to (111 … 111) from the ideal (that is,
VREF 1.5 LSB) after the midscale error has been adjusted out.
Positive Full-Scale Error Match
Positive full-scale error match is the difference in positive full-
scale error between the two ADCs.
ADC-to-ADC Isolation
ADC-to-ADC isolation is a measure of the level of crosstalk
between ADC A and ADC B. It is measured by applying a full-
scale 1 MHz sine wave signal to one of the two ADCs and
applying a full-scale signal of variable frequency to the other
ADC. The ADC-to-ADC isolation is defined as the ratio of the
power of the 1 MHz signal on the converted ADC to the power
of the noise signal on the other ADC that appears in the FFT.
The noise frequency on the unselected channel varies from
100 kHz to 2.5 MHz.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 5 kHz to 25 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of VIN+ and VIN
of frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency (f) in the ADC output.
PfS is the power at frequency (fS) in the ADC output.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±0.5 LSB, after the end of a conversion.
Signal-to-(Noise and Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-(noise and distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit
converter, SINAD is 86 dB.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7357 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357BCPZ | 功能描述:14 Bit Analog to Digital Converter 2 Input 2 SAR 18-LFCSP-WQ (5x4) 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 位數(shù):14 采樣率（每秒）:4.2M 輸入數(shù):2 輸入類型:差分 數(shù)據(jù)接口:SPI，DSP 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):2 架構(gòu):SAR 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:2.25 V ~ 2.75 V 電壓 - 電源，數(shù)字:2.25 V ~ 2.75 V 特性:同步采樣 工作溫度:-40°C ~ 85°C 封裝/外殼:18-WQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:18-LFCSP-WQ（5x4） 標(biāo)準(zhǔn)包裝:1 |
| AD7357BCPZ-RL | 功能描述:14 Bit Analog to Digital Converter 2 Input 2 SAR 18-LFCSP-WQ (5x4) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):14 采樣率（每秒）:4.2M 輸入數(shù):2 輸入類型:差分 數(shù)據(jù)接口:SPI，DSP 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):2 架構(gòu):SAR 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:2.25 V ~ 2.75 V 電壓 - 電源，數(shù)字:2.25 V ~ 2.75 V 特性:同步采樣 工作溫度:-40°C ~ 85°C 封裝/外殼:18-WQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:18-LFCSP-WQ（5x4） 標(biāo)準(zhǔn)包裝:5,000 |
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