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參數(shù)資料
| 型號： | AD7356BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 12BIT 5MSPS 16TSSOP |
| 設(shè)計資源： | DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 59mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，雙極 |
AD7356
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
VINA–
REFA
REFGND
VINB–
REFB
AGND
VINA+
VINB+
16
15
14
13
12
11
10
9
SCLK
SDATAA
SDATAB
CS
VDD
AGND
DGND
VDRIVE
AD7356
TOP VIEW
(Not to Scale)
06
50
5-
0
02
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
VINA+, VINA
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
3, 6
REFA, REFB
Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each
reference pin with a 10 μF capacitor. Provided the output is buffered, the on-chip reference can be taken from
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V
and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range
for the external reference is 2.048 V + 100 mV to VDD.
4
REFGND
Reference Ground. This is the ground reference point for the reference circuitry on the AD7356. Refer any
external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and
the REFA and REFB pins. Connect the REFGND pin to the AGND plane of a system.
5, 11
AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7356. All analog input
signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
7, 8
VINB, VINB+
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
9
VDD
Power Supply Input. The VDD range for the AD7356 is 2.5 V ± 10%. Decouple the supply to AGND with a 0.1 μF
capacitor in parallel with a 10 μF tantalum capacitor.
10
CS
Chip Select. Active low logic input. This input provides the dual functions of initiating conversions on the
AD7356 and framing the serial data transfer.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7356. Connect this pin to
the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
13, 14
SDATAB, SDATAA
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. To access the 12 bits of data from the AD7356, 14 SCLK falling edges are
required. The data simultaneously appears on both data output pins from the simultaneous conversions of
both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data
is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7356, then two trailing zeros
appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATA or SDATAB, the
data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both
ADCs to be gathered in serial format on either SDATAA or SDATAB.
A
15
SCLK
Serial Clock. Logic input. A serial clock input provides the serial clock for accessing the data from the AD7356.
This clock is also used as the clock source for the conversion process.
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
The voltage at this pin may be different than the voltage at VDD. The VDRIVE supply should be decoupled to
DGND with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor.
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| AD7356YRUZ | 功能描述:IC ADC DUAL 12BIT 5MSPS 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7356YRUZ-500RL7 | 功能描述:IC ADC DUAL 12BIT 5MSPS 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7356YRUZ-RL | 功能描述:IC ADC DUAL 12BIT 5MSPS 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7357 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
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