VINA–
參數(shù)資料
型號(hào)： AD7352BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/21頁(yè)
文件大?。?/td> 0K
描述： IC ADC DUAL 12BIT 3MSPS 16TSSOP
設(shè)計(jì)資源： DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 3M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 45mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD7352
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
VINA–
REFA
REFGND
VINB–
REFB
AGND
VINA+
VINB+
16
15
14
13
12
11
10
9
SCLK
SDATAA
SDATAB
CS
VDD
AGND
DGND
VDRIVE
AD7352
TOP VIEW
(Not to Scale)
0
704
4-
0
02
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
VINA+, VINA
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
3, 6
REFA, REFB
Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each
reference pin with a 10 μF capacitor. Provided the output is buffered, the on-chip reference can be taken from
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V
and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range
for the external reference is 2.048 V + 100 mV to VDD.
4
REFGND
Reference Ground. This is the ground reference point for the reference circuitry on the AD7352. Any external
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between
this pin and the REFA and REFB pins. Connect the REFGND pin to the AGND plane of a system.
5, 11
AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7352. Refer all analog input
signals to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
7, 8
VINB, VINB+
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
9
VDD
Power Supply Input. The VDD range for the AD7352 is 2.5 V ±10%. Decouple the supply to AGND with a 0.1 μF
capacitor in parallel with a 10 μF tantalum capacitor.
10
CS
Chip Select. Active low, logic input. This input provides the dual functions of initiating conversions on the
AD7352 and framing the serial data transfer.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7352. Connect this pin to
the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
13, 14
SDATAB, SDATAA
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. To access the 12 bits of data from the AD7352, 14 SCLK falling edges are
required. The data simultaneously appears on both data output pins from the simultaneous conversions of
both ADCs. The data stream consists of two leading zeros followed by 12 bits of conversion data. The data is
provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7352, then two trailing zeros
appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATA or SDATAB, the
data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both
ADCs to be gathered in serial format on either SDATA or SDATAB.
A
15
SCLK
Serial Clock, Logic Input. A serial clock input provides the serial clock for accessing the data from the AD7352.
This clock is also used as the clock source for the conversion process.
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
The voltage at this pin may be different than the voltage at VDD. The VDRIVE supply should be decoupled to
DGND with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor.
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